DE2447655A1 - CIRCUIT ARRANGEMENT FOR DECODING A CHROMINANCE SIGNAL - Google Patents

Description

Be se hreibu η g
to the patent application

the PA. INDESIT INDUSTRIA E LETTR OD OME ST IC I ITALIANA, S.p.A., Strada Piossasco Km. 17, Rivaita (Torino) / Italy

concerning:

"Circuit arrangement for decoding a chrominance signal"

The invention relates to a circuit arrangement for decoding a chrominance signal in a device capable of receiving a color television signal is designed, which signal is coded according to a system in which the modulation of a color subcarrier is a is subjected to periodic switching with line frequency, in particular according to the PAL system, so as to provide an identification signal to generate for the aforementioned switching with line frequency.

509818/0757

It is well known that color televisions are very complex and therefore expensive and relatively unreliable; there a more than satisfactory operating quality is now achieved efforts are now directed towards simplifying the circuitry in order to reduce costs and the likelihood of errors occurring. The object of the present invention is to provide a circuit arrangement for processing the chrominance signal in one device indicate the signal for the reception of a color television signal is designed which circuit arrangement should be particularly simple and effective.

This task is performed in a circuit arrangement for decoding a chrominance signal in a device, which is designed to receive a color television signal, which signal is encoded according to a system which the chrominance signal by means of a subcarrier modulation method is introduced with periodic switching with line frequency, whereby to ensure the correct phase position of the switching process a color subcarrier reference generator, a switching voltage generator and at least one synchronous demodulator, the first of which Input at least part of the chrominance signal and its a continuous oscillation generated by the reference generator can be fed to the second input, and are provided a circuit that generates a reverse voltage when its input signal amplitude is between a first and a second value, according to the invention proposal & g solved in that circuit means are provided in operative connection with the synchronous demodulator such that the amplitude of its output signal is between the first and second amplitude values when the switching voltage phasing it is wrong that the demodulator output with the

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Input of the circuit generating the reverse voltage is connected, which reverse voltage is connected to the switching voltage generator is supplied to reset it for the purpose of correcting the switching voltage phasing.

Further essential features of the invention emerge from the attached subclaims and the following Description of exemplary embodiments with reference to the accompanying drawings:

Fig. 1 shows a block diagram of a decoder

for a PAL system color television receiver according to the invention,

FIG. 2 shows a circuit diagram of blocks 8 and 2o according to FIGS. 1, and

Fig. 3 shows a block diagram of another embodiment of a decoder for a PAL system color television according to the invention.

Fig. 1 shows the block diagram of a decoder for a PAL system color television receiver. With 1 it is denotes the entire color carrier-frequency chrominance signal leading line from the corresponding bandpass amplifier comes from. The signal on line 1 reaches a gate 2, an adder circuit 3> a subtracting circuit 4 and a delay line 5 * which in the Frequency of the color subcarrier introduces a delay equal to the duration of a scan line. The output of the delay line 5 feeds the other inputs of the adding

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Circuit 3 and the subtracter circuit 4. With 6 denotes a line which carries a line frequency pulse train leads (I5625 Hz according to Italian standard), which pulses have a reasonable duration of e.g. Io microseconds; the impulses can do without further can be tapped at the horizontal deflection circle. The pulses on line 6 are fed to a pulse shaper 7, the pulses are generated with a suitable continuous amplitude and phase as well as a gate 8. The output of the Pulse shaper 7 is connected to gate 2, the output of which is in turn connected to a color subcarrier reference generator 9, which can be a selective quartz filter, for example. Of the The output of the generator 9 is fed to a synchronous demodulator Io which is connected to the output of the Adding circuit 5 and a circuit 11, which has a phase shift of 9 ° at the Parbo carrier frequency introduces. The output of the circuit 11 is in turn connected both directly and through a Phase shifter 12 which introduces a phase shift of 180 ° at the color subcarrier frequency with the two Inputs of an electronic switch Ij5, for example of the diode type, the control input of which is connected to an output of a line half-frequency switching voltage generator 14. The output of the switch 13 is connected to an input of a synchronous demodulator 15 * the other input is connected to the output of the subtracting circuit 4. The outputs of the demodulators Io and

15 are further connected to two electronic gates

16 or 17, at their outputs two color information

marked with the reference numerals 18 and I9 can be tapped.

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The output of the demodulator 15 is also connected to the input of a threshold detector circuit 2o, the output of which is fed to another input of the gate 8 will. The outputs of gate 8 go to the gates 16 and 17 and to the switching voltage generator 14. This Generator 14, which is, for example, a bistable multivibrator, has an output which is connected to an input of the pulse shaper 7.

Referring to Figure 2, there is a circuit diagram for the threshold detector circuit 2o and the gate 8 shown in FIG. The coloring information I9 reaches a capacitor 30, which is connected with its other coating to the cathode of a diode 31 and via a resistor 32 to ground is, so that a threshold detector results. The anode of diode 3I is connected to the base of an NPN transistor 33, with the wiper of a potentiometer 34 and a capacitor 35 with ground. The emitter of transistor 33 is connected to ground, while its collector with the collector of an NPN transistor.s 36, one a Supply voltage + V carrying terminal is connected via a resistor 37 and to an output line 38, those to gates 16 and I7 and to the switching voltage generator 14 leads. The emitter of transistor 36 is connected to ground, while its base, which is via a resistor 39 is connected to ground, the pulses from line 6 via a Capacitor 4o receives. The potentiometer 34 is connected between ground and the voltage + V. The operation of the decoder circuit according to Fig. 1 in the embodiment according to the invention is the following.

The blocks 7, 2, lo, 15, 5, 4, 3, 11, 12, 13, 14 and 9 form, without the connection between the generator 14 and the pulse shaper J, a normal delay

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-C-

leltungs PAL decoder. As a result of the mentioned connection between the generator 14 and the pulse shaper 7, which forms part of the circuit according to the invention for resetting the generator 14, the pulses from line 6, which are fed to the gate 2 for the purpose of opening it during the time periods in which the color sync signals (bursts) are transmitted, not the line repetition frequency, but only half of this, ie only every second line results in a pulse. Accordingly, the generator 9 receives only the synchro signals of the even-numbered lines or those of the odd-numbered lines corresponding to the switching phase of the generator 14. The generator 9 is designed so that it supplies a continuous oscillation which is suitably out of phase with the SynchroSignaIeη such that when the switching phase of the generator 14 is correct, the phase of the oscillation generated by the generator 9 is correct and accordingly also that of the demodulations that take place in the demodulators Io and 15. The color information is then the BY information and the color information 19 is the RY information. The latter is detected by the detector 2o, the gate circuit 8 is activated, and the pulses from 6 go to the generator 14, which keeps it in synchronism and to the gates 16 and 17, which in this way isolate the outputs during the line return, to which the color information l8 and I9 are present.

On the other hand, if the phase of the generator l * f is wrong, the generator I9 receives the color sync signals of the wrong lines that are 90 ° out of phase. The generated oscillation is then also out of phase

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scrape around the same angle and practically surrenders no. Signal at the outputs of the demodulators en Io and I5. The detector 2o no longer receives a signal or only an insufficient signal, the gate circuit 8 is blocked, and as a result the generator 14 is also blocked until it is back in phase. The gates 16 and I7 also remain closed until the correct phase position is restored.

In the case of receiving a monochromatic signal Since there is no chrominance signal, the gate circuit 8, the gates 16 and I7 and the generator 14 remain automatically blocked, and accordingly the color suppressing function is also blocked achieved. If desired, it is possible to measure the output of the demodulator Io with a second threshold detector similar to the detector 2o to connect and the outputs of the two detectors to the circuit 8 via to connect an OR circuit. Achieved this way an even more reliable mode of operation.

In detail, the operation of the rocker switch 2o and the gate circuit 8 according to FIG. 2 proceed as follows. The color signal I9 the diode 31 is supplied. The resistor closes the DC "voltage detector circuit. The capacitor 35 filters the rectified voltage applied to the base of transistor 33. The potentiometer 34 is used to adjust the intervention threshold of the threshold circuit. At the Base of transistor 36 appear across the capacitor 4o the pulses of 6 with positive polarity and an amplitude sufficient to turn transistor 36 on. The base circuit is closed for the direct current through the resistor 39. The control voltage is supplied by means of the line 38 for the gate circuits 16 and I7 and the generator

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14 removed; this control voltage is low (about 0.4 volts) during the presence of the pulses from 6 (because transistor 36 has turned on) and high (corresponding to + V) in the intervals between the pulses, if the color information 19 is large enough, the threshold voltage , set by the potentiometer ~ $ Κ on the capacitor 35, to be overcome and the transistor 33 to be blocked via the diode 3I. If, on the other hand, there is no signal I9 or only a signal I9 with too low an amplitude, the transistor 33 remains permanently switched on, the voltage on the line 38 remains low and the gate circuits 16 and I7 with the switching voltage generator 14 remain blocked.

Various modifications can be made to the circuit arrangement described. For example, can the delay line 5 instead of introducing a delay for the chrominance signal equal to the duration of only one scanning line, a delay equal to the duration of one introduce odd number of lines (e.g. 3 or 5) · The detector threshold circuit 2o can instead of a normal peak amplitude detector comprise a double or peak-to-peak detector, which is known per se is and is therefore readily available to the person skilled in the art and which is followed by a comparator with a predetermined threshold. In this way the signal which is supplied by the detector arrangement is independent of the sign the applied voltage (positive or negative) and in the present case is no longer a function of the color of the transmitted scene, as is the case with simple amplitude detection, from which there are obvious operational advantages.

The circuit according to FIG. 3 differs from that according to FIG. 1 in that two further demodulators 5o and 51 are present which are connected to do the

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receive the same signal that is transmitted to the demodulators Io or. The demodulator 50 receives the signal at the output of the phase shifter circuit 11 as a subcarrier, while the demodulator 51 receives the signal at the output of the generator 9 as ^{a subcarrier.} The outputs of the demodulators 50 and 51 then pass to assigned detector threshold circuits 52 and 53, the outputs of which are added in an OR gate 54. The output of the OR gate 54 reaches the input of a differential circuit 55 * at the other input of which the output signal of an OR gate 56 is present. The outputs of the threshold detector 2o, connected downstream of the demodulator I5, and of the threshold detector 57 *, connected downstream of the demodulator lo, are connected to the input of the OR gate 56.

With the circuit arrangement according to FIG. 3, in which four synchronous demodulators (lo, I5, 50 and ^ l) are provided, one obtains a very good operation for the identification even under the most difficult signal conditions.

At the output of the demodulators 5o and 5I is if the phase of the generator 14 is correct, no signal, and accordingly no signal appears at the output of the OR gate 54 so that the differential circuit 55 only receives the signal from the output of the OR gate 56 and the signal at the output of the circuit 55 itself controls the activation of the gate circuit 8, which the transmission allows the pulses from 6 to the switching voltage generator 14, with which this is kept synchronized.

On the other hand, if the shift phase is wrong, get a detected signal from demodulators 50 and 5I » and an output signal is then obtained from the OR gate 5 ^. This output signal is fed to the differential circuit 55

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509818/0757

fed, which controls the gate circuit 8 in the blocking state and consequently blocks the generator 14 until the correct switching phase is restored.

Accordingly, this circuit arrangement results in reliable operation of the identification itself the most difficult signal conditions.

The advantages of the circuit arrangement according to the invention clearly emerge from the above description. It it goes without saying that those skilled in the art can readily make and implement numerous modifications without relying on the Basic idea of the present invention deviate.

Patent claims:

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509818/0757

Claims (13)

Claims Circuit arrangement for the decoding of a chrominance signal in a device which is intended for the reception of a color television signal is designed, which signal is encoded according to a system in which the chrominance signal by means of a subcarrier modulation method is introduced with periodic switching with line frequency, whereby to ensure the correct Phase position of the switching process a color subcarrier reference generator, a switching voltage generator and at least one synchronous demodulator, the first input of which has at least one part of the chrominance signal and its second input one of the Reference generator generated continuous oscillation are supplied, and a circuit that has a reverse voltage generated when its input signal amplitude is between a first and a second value, characterized in that, that circuit means are provided in operative connection with the synchronous demodulator such that the amplitude of its output signal lies between the first and second amplitude values when the switching voltage phasing is incorrect that the Demodulator output with the input of the reverse voltage generating Circuit is connected, which reverse voltage is fed to the switching voltage generator in order to reverse it. add to correct the switching voltage phase position. 2. Circuit arrangement according to claim 1, characterized in that the circuit means has a first electronic gate which is controlled by the switching voltage generator and is connected in the path along which the color synchronization signals, introduced in the chrominance signal, to the color subcarrier reference generator be transmitted. - 12 - 509818/0757 3. Circuit arrangement according to claim 2, characterized in that the first gate simultaneously from the switching voltage generator and of line repetition frequency pulses is controlled so that it opens every other line during the time interval in which the color synchronizing signals are present in the incoming chrominance signal. K. Circuit arrangement according to one of the preceding claims, characterized in that the circuit means comprise a delay line for delaying the chrominance signal by a time interval substantially equal to the duration of (2n + 1) scanning lines, where η is an integer, and that the signal from the output of the delay line and the chrominance signal are fed to an adding or subtracting circuit, the output of which is fed to the synchronous demodulator. 5. Circuit arrangement according to one of the preceding claims, characterized in that it has a second synchronous demodulator comprises with a first input to which at least a part of the chrominance signal is present and a second input, to which a continuous oscillation is fed via phase shift circuits is done by the reference generator, and that the output of the first and the second demodulator to the input of the blocking voltage generator fed through an OR circuit will. 6. Circuit arrangement according to claim 5 » characterized in that a third and a fourth synchronous demodulator are provided, which receive a subcarrier with the same phase from the reference generator, that the second and fourth demodulator a subcarrier in 9 °° phase relation with respect to the first and third demodulator-receiving subcarrier received that the outputs of the first and the - 13 509818/0757 second demodulator and the outputs of the third and fourth demodulator Schwellerfi ^ detector circuits of the reverse voltage generating circuit are fed, that the outputs of the detector circuits are added to each other in pairs in OR gates, that the outputs of the OR gates are fed to the inputs of a differential circuit s ^ nd and that the output of the differential circuit is in turn connected to the input of a gate that is in blocking connection with the switching voltage generator. 7. 'Circuit arrangement according to one of the preceding claims, characterized in that the reverse voltage generating circuit at least one double half-wave amplitude detector circuit includes. 8. Circuit arrangement according to one of the preceding claims, characterized in that the first and / or second demodulator is also designed for deriving the demodulated color signal (s) from the chrominance signal are. 9. Circuit arrangement according to claim 8, characterized in that that it comprises gates controlled by the reverse voltage, which receive the signal from the output of the first and second Block demodulator. 10. Circuit arrangement according to one or more of the The preceding claims, characterized in that the color subcarrier reference voltage generator is a selective Quartz filter includes * 11. Circuit arrangement according to one or more of the preceding claims, characterized in that the Switching voltage generator is a bistable multivibrator. ■ - 14-- 509818/0757 12. Circuit arrangement according to one or more of the preceding claims characterized in that the device is a color television receiver. 13. Circuit arrangement according to one or more of the preceding Claims, characterized in that the color television system is the PAL system. 509818/0757 Blank page