GB1471736A - - Google Patents

Info

Publication number
GB1471736A
GB1471736A GB2205474A GB2205474A GB1471736A GB 1471736 A GB1471736 A GB 1471736A GB 2205474 A GB2205474 A GB 2205474A GB 2205474 A GB2205474 A GB 2205474A GB 1471736 A GB1471736 A GB 1471736A
Authority
GB
United Kingdom
Prior art keywords
degrees
face
crystallographic
growth rate
orientation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2205474A
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1471736A publication Critical patent/GB1471736A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2924—Structures
    • H10P14/2925—Surface structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2926—Crystal orientations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3466—Crystal orientation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/901—Levitation, reduced gravity, microgravity, space
    • Y10S117/902—Specified orientation, shape, crystallography, or size of seed or substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/973—Substrate orientation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Recrystallisation Techniques (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
GB2205474A 1973-05-18 1974-05-17 Expired GB1471736A (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7306948A NL7306948A (enExample) 1973-05-18 1973-05-18

Publications (1)

Publication Number Publication Date
GB1471736A true GB1471736A (enExample) 1977-04-27

Family

ID=19818883

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2205474A Expired GB1471736A (enExample) 1973-05-18 1974-05-17

Country Status (9)

Country Link
US (1) US4000019A (enExample)
JP (1) JPS5522022B2 (enExample)
AU (1) AU6912674A (enExample)
CH (1) CH588163A5 (enExample)
DE (1) DE2423816A1 (enExample)
FR (1) FR2230083B1 (enExample)
GB (1) GB1471736A (enExample)
IT (1) IT1012429B (enExample)
NL (1) NL7306948A (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2828607C3 (de) * 1977-06-29 1982-08-12 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Halbleitervorrichtung
US4278987A (en) * 1977-10-17 1981-07-14 Hitachi, Ltd. Junction isolated IC with thick EPI portion having sides at least 20 degrees from (110) orientations
EP0020135A1 (en) * 1979-05-29 1980-12-10 Massachusetts Institute Of Technology Three-dimensional integration by graphoepitaxy
JPS5691903U (enExample) * 1979-12-17 1981-07-22
JPS5694732A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Semiconductor substrate
US4355072A (en) * 1980-02-12 1982-10-19 U.S. Philips Corporation Magnetic hexagonal ferrite layer on a nonmagnetic hexagonal mixed crystal substrate
JPS5930696A (ja) * 1982-08-05 1984-02-18 本多　浩 汎用位置決めと速度制御が可能なエアシリンダと補助駆動装置からなる複合アクチユエ−タ
JPS6290095U (enExample) * 1985-11-22 1987-06-09
JPS6339396U (enExample) * 1986-09-01 1988-03-14
JPH01151144U (enExample) * 1988-04-12 1989-10-18
JP2603342B2 (ja) * 1988-10-02 1997-04-23 キヤノン株式会社 結晶物品及びその形成方法
JP2570646B2 (ja) * 1994-12-13 1997-01-08 日本電気株式会社 Ｓｉベ−ス半導体結晶基板及びその製造方法
US6171966B1 (en) * 1996-08-15 2001-01-09 Applied Materials, Inc. Delineation pattern for epitaxial depositions
DE19915156A1 (de) * 1999-03-27 2000-09-28 Inst Halbleiterphysik Gmbh Verfahren zur Herstellung dünner gleichförmiger Oxidschichten auf Silizium-Oberflächen
TW483171B (en) * 2000-03-16 2002-04-11 Trw Inc Ultra high speed heterojunction bipolar transistor having a cantilevered base.
JP5075469B2 (ja) 2007-05-08 2012-11-21 株式会社オーディオテクニカ グースネック型マイクロホン
US8389099B1 (en) 2007-06-01 2013-03-05 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
US8348720B1 (en) 2007-06-19 2013-01-08 Rubicon Technology, Inc. Ultra-flat, high throughput wafer lapping process

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3325314A (en) * 1961-10-27 1967-06-13 Siemens Ag Semi-conductor product and method for making same
US3379584A (en) * 1964-09-04 1968-04-23 Texas Instruments Inc Semiconductor wafer with at least one epitaxial layer and methods of making same
US3476592A (en) * 1966-01-14 1969-11-04 Ibm Method for producing improved epitaxial films
US3556875A (en) * 1967-01-03 1971-01-19 Philco Ford Corp Process for epitaxially growing gallium arsenide on germanium
US3728166A (en) * 1967-01-11 1973-04-17 Ibm Semiconductor device fabrication method and product thereby
US3697318A (en) * 1967-05-23 1972-10-10 Ibm Monolithic integrated structure including fabrication thereof
JPS4830787B1 (enExample) * 1967-12-28 1973-09-22
NL171309C (nl) * 1970-03-02 1983-03-01 Hitachi Ltd Werkwijze voor de vervaardiging van een halfgeleiderlichaam, waarbij een laag van siliciumdioxyde wordt gevormd op een oppervlak van een monokristallijn lichaam van silicium.

Also Published As

Publication number Publication date
FR2230083B1 (enExample) 1977-10-21
IT1012429B (it) 1977-03-10
JPS5020674A (enExample) 1975-03-05
JPS5522022B2 (enExample) 1980-06-13
AU6912674A (en) 1975-11-20
FR2230083A1 (enExample) 1974-12-13
US4000019A (en) 1976-12-28
CH588163A5 (enExample) 1977-05-31
NL7306948A (enExample) 1974-11-20
DE2423816A1 (de) 1974-12-05

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee