GB1413161A - Process for manufacturing semiconductor devices - Google Patents

Process for manufacturing semiconductor devices

Info

Publication number
GB1413161A
GB1413161A GB4564772A GB4564772A GB1413161A GB 1413161 A GB1413161 A GB 1413161A GB 4564772 A GB4564772 A GB 4564772A GB 4564772 A GB4564772 A GB 4564772A GB 1413161 A GB1413161 A GB 1413161A
Authority
GB
United Kingdom
Prior art keywords
layer
substrate
insulant
deposited
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4564772A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of GB1413161A publication Critical patent/GB1413161A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/018—Manufacture or treatment of isolation regions comprising dielectric materials using selective deposition of crystalline silicon, e.g. using epitaxial growth of silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/969—Simultaneous formation of monocrystalline and polycrystalline regions

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
GB4564772A 1971-10-11 1972-10-04 Process for manufacturing semiconductor devices Expired GB1413161A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP46080047A JPS5232234B2 (enExample) 1971-10-11 1971-10-11

Publications (1)

Publication Number Publication Date
GB1413161A true GB1413161A (en) 1975-11-05

Family

ID=13707313

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4564772A Expired GB1413161A (en) 1971-10-11 1972-10-04 Process for manufacturing semiconductor devices

Country Status (4)

Country Link
US (1) US3849270A (enExample)
JP (1) JPS5232234B2 (enExample)
DE (2) DE2249832C3 (enExample)
GB (1) GB1413161A (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583380B2 (ja) * 1977-03-04 1983-01-21 株式会社日立製作所 半導体装置とその製造方法
JPS5893261A (ja) * 1981-11-30 1983-06-02 Toshiba Corp 半導体装置の製造方法
WO1990000476A1 (en) * 1988-07-12 1990-01-25 The Regents Of The University Of California Planarized interconnect etchback
US5256565A (en) * 1989-05-08 1993-10-26 The United States Of America As Represented By The United States Department Of Energy Electrochemical planarization
US5096550A (en) * 1990-10-15 1992-03-17 The United States Of America As Represented By The United States Department Of Energy Method and apparatus for spatially uniform electropolishing and electrolytic etching
US6315883B1 (en) 1998-10-26 2001-11-13 Novellus Systems, Inc. Electroplanarization of large and small damascene features using diffusion barriers and electropolishing
US7449098B1 (en) 1999-10-05 2008-11-11 Novellus Systems, Inc. Method for planar electroplating
US6709565B2 (en) 1998-10-26 2004-03-23 Novellus Systems, Inc. Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation
US7531079B1 (en) 1998-10-26 2009-05-12 Novellus Systems, Inc. Method and apparatus for uniform electropolishing of damascene IC structures by selective agitation
US6495442B1 (en) * 2000-10-18 2002-12-17 Magic Corporation Post passivation interconnection schemes on top of the IC chips
US6653226B1 (en) 2001-01-09 2003-11-25 Novellus Systems, Inc. Method for electrochemical planarization of metal surfaces
TW200308009A (en) * 2002-04-09 2003-12-16 Rensselaer Polytech Inst Electrochemical planarization of metal feature surfaces
US7799200B1 (en) 2002-07-29 2010-09-21 Novellus Systems, Inc. Selective electrochemical accelerator removal
US8530359B2 (en) 2003-10-20 2013-09-10 Novellus Systems, Inc. Modulated metal removal using localized wet etching
US8158532B2 (en) 2003-10-20 2012-04-17 Novellus Systems, Inc. Topography reduction and control by selective accelerator removal
US8168540B1 (en) 2009-12-29 2012-05-01 Novellus Systems, Inc. Methods and apparatus for depositing copper on tungsten

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3169892A (en) * 1959-04-08 1965-02-16 Jerome H Lemelson Method of making a multi-layer electrical circuit
GB1048424A (en) * 1963-08-28 1966-11-16 Int Standard Electric Corp Improvements in or relating to semiconductor devices
US3372063A (en) * 1964-12-22 1968-03-05 Hitachi Ltd Method for manufacturing at least one electrically isolated region of a semiconductive material
US3409523A (en) * 1966-03-10 1968-11-05 Bell Telephone Labor Inc Electroetching an aluminum plated semiconductor in a tetraalkylammonium hydroxide electrolyte
FR96113E (fr) * 1967-12-06 1972-05-19 Ibm Dispositif semi-conducteur.
NL7101307A (enExample) * 1970-02-03 1971-08-05

Also Published As

Publication number Publication date
JPS5232234B2 (enExample) 1977-08-19
JPS4845185A (enExample) 1973-06-28
DE2265257A1 (de) 1977-02-10
DE2249832A1 (de) 1973-04-19
DE2249832C3 (de) 1982-02-18
US3849270A (en) 1974-11-19
DE2249832B2 (de) 1977-06-02
DE2265257C2 (de) 1983-10-27

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee