GB1345858A - Flip-flop stages - Google Patents

Abstract

1345858 Bistable logic circuits VDO ADOLF SCHINDLING GmbH 27 Oct 1972 [9 Nov 1971] 49677/72 Heading H3P [Also in Division G4] The effects of interference voltages on a bistable 1 comprising four logic gates 5, 6, 7, 8, are reduced by introducing time constants 9, 10 into the cross-coupling of gates 5, 6, and relatively larger time constants 13, 14 into further feedback circuits from the outputs of gates 5, 6, to respective inputs of gates 8, 7. Four such bistables 1, 2, 3, 4, constitute a counter, and a further discrimination against noise is provided by a pulse shaper 12. This includes 1.p. filters 20, 21 and Schmitt triggers 18, 19 which drive a NAND gate 22. The gates used in the bistables are NAND gates. The time constants 13, 14 are preferably ten times those 9, 10. In operation, a 1 from an inverter 11 when NAND 22 output goes to 0 in response to an input 21, makes the inputs to NAND 7 all 1, the other two inputs being at 1 because of 1 from a NAND 16 and a 1 from NAND 6 output via RC 14. One input of NAND 5 therefore goes to 0 and its output to 1, changing the state of cross-coupled gates 5, 6. The 1 fed back to NAND 8 input is slowed by RC 13 so that the input 1 from 11 has ceased before the fed-back 1 becomes effective. The second pulse 1 from 11 then makes both inputs to NAND 8 because 1 and its output 0 changes NAND 6 output to 1 to reset the crosscoupled pair 5, 6. In this case RC 14 slows the feed-back of 1 to NAND 7 input. The second 1 from 11 also causes both inputs to a NAND 15 to be 1, and an output 1 goes to the second stage 2. The NAND 16, which supplies the third input to all the NAND gates 7, receives as inputs: the output of the NAND 5 of the stages 1 and 4, the input pulse from 11, and a 1 or 0 from switch 17. If switch 17 supplies a 1, decimal counting is effected, and if a 0, binary counting.