GB1327306A - Method of masking a surface of a semiconductive sub strate - Google Patents

Method of masking a surface of a semiconductive sub strate

Info

Publication number
GB1327306A
GB1327306A GB845571A GB1327306DA GB1327306A GB 1327306 A GB1327306 A GB 1327306A GB 845571 A GB845571 A GB 845571A GB 1327306D A GB1327306D A GB 1327306DA GB 1327306 A GB1327306 A GB 1327306A
Authority
GB
United Kingdom
Prior art keywords
resist
photo
windows
layer
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB845571A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Publication of GB1327306A publication Critical patent/GB1327306A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Weting (AREA)

Abstract

1327306 Photographic process PLESSEY CO Ltd 20 March 1972 [1 April 1971] 8455/71 Heading G2C [Also in Division H1] A semi-conductor substrate, e.g. a Si integrated circuit wafer 3 provided with an oxide coating 1; is coated with a first layer 5 of a photo-resist in which windows are etched, and then a second layer of photo-resist is provided and etched so as to leave only portions 8 which partly overlie the windows in the first layer 5. Windows 9 are thus formed through the combined photo-resist layer 5/8, which windows have a smaller width than that of the corresponding windows in the photomask used to define them. Preferably the same photo-mask is used to shape both photo-resist layers, the mask being displaced laterally between the respective photo-resist exposure stages by a distance equal to the desired width of the windows 9. The first photo-resist layer 5 in this case consists of a negative resist while the second layer is of a positive resist. The oxide coating 1 may then be selectively etched through the windows 9 before the combined photo-resist layer 5/8 is removed.
GB845571A 1972-03-20 1972-03-20 Method of masking a surface of a semiconductive sub strate Expired GB1327306A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB845571 1972-03-20

Publications (1)

Publication Number Publication Date
GB1327306A true GB1327306A (en) 1973-08-22

Family

ID=9852824

Family Applications (1)

Application Number Title Priority Date Filing Date
GB845571A Expired GB1327306A (en) 1972-03-20 1972-03-20 Method of masking a surface of a semiconductive sub strate

Country Status (1)

Country Link
GB (1) GB1327306A (en)

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees