GB1307808A - Circuitry connected to receive a set of at least three identical binary signals of which one must always appear at the output of the circuitry - Google Patents

Circuitry connected to receive a set of at least three identical binary signals of which one must always appear at the output of the circuitry

Info

Publication number
GB1307808A
GB1307808A GB2268671A GB2268671A GB1307808A GB 1307808 A GB1307808 A GB 1307808A GB 2268671 A GB2268671 A GB 2268671A GB 2268671 A GB2268671 A GB 2268671A GB 1307808 A GB1307808 A GB 1307808A
Authority
GB
United Kingdom
Prior art keywords
erect
signals
inverted
pulses
circuitry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2268671A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LANNIONNAISE DELECTRONIQUE SOC
Original Assignee
LANNIONNAISE DELECTRONIQUE SOC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LANNIONNAISE DELECTRONIQUE SOC filed Critical LANNIONNAISE DELECTRONIQUE SOC
Publication of GB1307808A publication Critical patent/GB1307808A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1604—Error detection or correction of the data by redundancy in hardware where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00392—Modifications for increasing the reliability for protection by circuit redundancy
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Amplifiers (AREA)
  • Hardware Redundancy (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
GB2268671A 1970-02-27 1971-04-19 Circuitry connected to receive a set of at least three identical binary signals of which one must always appear at the output of the circuitry Expired GB1307808A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7007201A FR2080251A5 (enrdf_load_stackoverflow) 1970-02-27 1970-02-27

Publications (1)

Publication Number Publication Date
GB1307808A true GB1307808A (en) 1973-02-21

Family

ID=9051427

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2268671A Expired GB1307808A (en) 1970-02-27 1971-04-19 Circuitry connected to receive a set of at least three identical binary signals of which one must always appear at the output of the circuitry

Country Status (12)

Country Link
US (1) US3686657A (enrdf_load_stackoverflow)
JP (2) JPS543336B1 (enrdf_load_stackoverflow)
BE (1) BE762927A (enrdf_load_stackoverflow)
CA (1) CA971638A (enrdf_load_stackoverflow)
CH (1) CH530125A (enrdf_load_stackoverflow)
DE (1) DE2109023C2 (enrdf_load_stackoverflow)
ES (1) ES388695A1 (enrdf_load_stackoverflow)
FR (1) FR2080251A5 (enrdf_load_stackoverflow)
GB (1) GB1307808A (enrdf_load_stackoverflow)
NL (1) NL7102304A (enrdf_load_stackoverflow)
SE (1) SE362561B (enrdf_load_stackoverflow)
SU (1) SU382317A3 (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH617014A5 (enrdf_load_stackoverflow) * 1977-03-04 1980-04-30 Bbc Brown Boveri & Cie
FR2390856A1 (fr) * 1977-05-10 1978-12-08 Lannionnais Electronique Base de temps
GB2178926A (en) * 1985-08-09 1987-02-18 Plessey Co Plc Clock signal selection and security arrangements
JP2510750B2 (ja) * 1990-03-16 1996-06-26 株式会社日立製作所 フォ―ルト・トレラント・システム及びその冗長系間の同期方法並びに多重化クロツク発振器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DD66438A (enrdf_load_stackoverflow) *
US3496539A (en) * 1966-07-15 1970-02-17 Itt Comparator using resistor-diode logic
US3458822A (en) * 1966-11-17 1969-07-29 Bell Telephone Labor Inc Clock pulse failure detector
US3522455A (en) * 1967-07-27 1970-08-04 Bendix Corp Method and means of synchronizing timing pulses of a three channel triplicated system

Also Published As

Publication number Publication date
SE362561B (enrdf_load_stackoverflow) 1973-12-10
DE2109023C2 (de) 1983-02-10
CH530125A (fr) 1972-10-31
BE762927A (fr) 1971-08-16
DE2109023A1 (de) 1971-09-09
FR2080251A5 (enrdf_load_stackoverflow) 1971-11-12
US3686657A (en) 1972-08-22
SU382317A3 (enrdf_load_stackoverflow) 1973-05-22
NL7102304A (enrdf_load_stackoverflow) 1971-08-31
JPS543336B1 (enrdf_load_stackoverflow) 1979-02-21
JPS462103A (enrdf_load_stackoverflow) 1971-10-11
CA971638A (en) 1975-07-22
ES388695A1 (es) 1973-05-16

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee