GB1357862A - Digital data store arrangements - Google Patents

Abstract

1357862 Dynamic binary store SIEMENS AG 16 Aug 1972 [30 Aug 1971] 38299/72 Heading H3T The invention relates to a fail-safe binary store in which 0 and 1 signals are respectively represented at input and output by opposite phases of a square wave signal. According to the invention the store comprises a master-slave bi-stable circuit MA, SL fed at its clock inputs, from terminal B, with opposite phase double frequency pulses and controlled by a majority logic circuit M, E receiving two input signals El, E2 and a feedback signal E3. As described the logic circuit is an inverting transistor circuit (Fig. 3, not shown). When both inputs E1 and E2 are in phase they control the logic output and cause the final output to follow, in phase. When E1 and E2 are out of phase the logic circuit is effectively controlled by the feedback and the output continues in the same phase as previously. A failure indicator may detect a non-alternating state of the output. Further, two stores may be operated in parallel (Fig. 4, not shown) with signals in opposite phase; an exlusive OR circuit (U) detecting a failure causing in-phase outputs. When integrated construction is used, separate clock lines improve failure detection and two opposite phase clock lines may be used, one including an inverter so that if the clock on both lines fails the two outputs are in phase and failure is detected by the "exclusive OR" circuit.