DE2143375B1 - Electronic memory element for digital data processing systems with a high level of error security, in particular for railway safety - Google Patents

Description

ORIGINAL INSPECTED

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second, the slave. With these flip leads, the inputs are labeled R and S , which lead to particularly small and price flops. cheap modern building blocks.

Both tilting stages are designed so that they are only then embodiments of the invention according to

the signals at their inputs R and S are explained in more detail with reference to the drawing. The record when 5 figures show in detail at an associated clock input:

a 1 signal is present. The clock signal changes peri- Fig. 1 the basic circuit of an electronic

odically between the two states 0 and 1. If storage element for square-wave signal voltage and the Clock signal changes from 1 to 0, the master is gene with a phase difference of 180 ° to the Unfor any further signal acceptance is blocked while the two logical values of the switch are differentiated Slave over- io variable the signals output by the master,

takes, on the other hand, the master takes the clock signal F i g. 2 in several diagram lines the temporal

change from 0 to 1 information. This course of different signal voltages,

Triggering of the two flip-flops can be done by two F i g. 3 a circuit arrangement for the majority

different clock signals that do not coincide, decision with signal inversion and

take place. However, only one clock signal is thus supplied to 15 F i g. 4 a two-channel memory module that must be, the required for the slave from two identical memory elements and one is the Clock signal with the help of a clock negator from the device monitoring the signal equivalence.

Master provided clock signal derived. The schematic arrangement according to FIG. 1 shows a

The desire for a system-compatible electronic storage element, which has an iW master-slave flip-flop as a storage element or a combination thereof. This consists of a master-flip-set two-channel memory module as a supplementary flop MA and a slave switch connected downstream of the known safety circuit to the through-flip-flop SL. The logic operations that lead to the control of the two flip-flops are fulfilled according to the invention via the T measure in that the S input of the master directs the master MA and the slave SL via a direct and its i? Input via a negation element 25 negation element JVl supplied indirectly. Furthermore, an assembly forming a majority decision with signal inverter assembly ME with three inputs E1, E 2 and E 3 is connected which has three inputs due to the mentioned three inputs, two of which are for the binary inputs existing signal voltages a multiple switching variable in the form of a square-wave unit decision with signal inversion. Signal voltages are provided, the logic of which is 30 The output A of the assembly ME is set on the one hand with values due to a phase difference of 180 ° to the input SMA of the master MA and on the other hand, and the third input with the one via a negation element JV 2 with the other Input output of the slave is connected, which is connected to the 5-input RMA of the master MA . A gene is also assigned, and that the embodiment of the invention required for triggering is conceivable in which the double predetermined sequence of the module ME does not invert in the particular clock signal. Then the frequency of the square-wave signal voltages has the negation element JV 2 not with the input whereby the trailing edges of the clock signal coincide in time , but with the other input SMA coincide with the edges of the signal voltages. Masters MyI connected. The RMA input of the

The particular advantage of such an electronic master MA is in that case directly linked to the appearance of a memory element for rectangular signal output A of the voltages that make the majority decision, that it is connected to the structure of an assembly ME . The output QS of the switching mechanism with logic elements of the well-known memory element is included in a feedback branch of the th safety circuit for performing logical i? 5 master-slave flip-flops and for this connection additionally with two-channel dynamic purpose with the input E3 of the assembly ME verschen memory modules with each other antivalen- 45 bound. The other two inputs £ 1 and E 2 allow signals on the two channels, whereby this module is acted upon by each rectangular memory module from two of these memory elements signal voltages, which consist of the switching variables, whose equivalent inputs correspond to orderly, with a phase difference of just Operation with complementary signal voltages 180 ° to differentiate between the two logical values. The clock signals, which are supplied via the terminal T, of each memory module are connected to a device that monitors the signal and has twice the value of that repetition frequency and that is provided for the signal voltages.
whereby an automatic low-delay and The phase position of the clock signal to the signal span

safe error message is enabled. The storage is chosen so that the trailing edges of the clock element therefore do not need to coincide in time with the edges of the 55 after the fail-safe print signal zip to be built. Any falsification of the ever- signal voltages.

certain memory contents as a result of a Störbeeinflus- F i g. 2 shows in several diagram lines the time

Solution or any component failure on borrowed course of several electrical rectangular one channel is independent of the respective switching voltages. The diagram state of the memory module or the memory line labeled LT shows the course of the clock signals with leading edges VE and reliably reported as an error at the terminal Γ (FIG. 1) elements no later than after one clock cycle. This trailing edge property RE. The presence of the enables the module to also be used for counters or leading edges VE, that is to say at the transition from logic 0 shift registers, when the master MA takes the fail-safe facilities required for such a shift register to 1. The 65 input signals fed to it; the two-channel memory module including the slave SL is blocked. This takes over the device monitoring the master's signal equivalence, and can output all applications as an integrated circuit for MA via its outputs QM1 and QM 2, in each case at the trailing edges RE of the

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Clock signals, i.e. the transition from logic 1 to 0. Time ti low potential, which is synonymous with

During this time the Master MA is blocked. is logical 1. At the next leading edge VE des

The diagram lines LO and LL show the clock signal is taken over by the master MA over its course of the two square-wave signal voltages, input SMA from output A logic 0 with high potential shifted by 180 ° against each other in phase 5 and through its input RMA low potential; these are and the two possible logical values 0 are then at the outputs QMl and QM represent 2 and 1 of the switching variables. The slide available. In the course of the following trailing edge program lines LEI, LE2 and LE3 , the three inputs RE of the clock signal (after point in time 1 2) are assigned to el, E2 and E3 of the assembly ME forming the majority decision slave SL, the separation offered by the master MA . For io signals, so that seen in terms of time after the times mentioned, the input El has a low potential trailing edge RE of the clock signal at the output QS of the and the input E2 has a high potential. When comparing slaves SL, there is still a high potential, which is synonymous with logic 1 with the lines LO and LL in the diagram (cf. the course of the signal voltages in the diagram, lines LE 3 and LL). The set command, i.e. logical 1, that the input El is the logical 1 and the input 15 on input El, remains until the time * 3 received- E2 receives the logical 0. From this point onwards, the input from the slave SL via its output QS is present at the input E 2, a signal voltage which represents the value of logic 0 level and the signal supplied to input E 3 with dem. This is the one between the points in time that is on input E 2 . Thus, 12 and 13 given setting command to be withdrawn, and also performs the input E3 logic 0. These from the off ao between times 13 and t4 is the gear QS output information indicates that the inputs El and E2 of the module ME same storage member in the reset State. The signal configuration as between the times to assembly ME to form a majority decision and t2. The output QS of the slave SL , however, still receives logic 1 via the inputs at the time ίο; the memory element is and E2 and E3 that of the logical 0 at the time 25 remains set. This means that input E3 also has a correspondingly high potential. This still results in logical 1. When considering the slide majority decision and inversion for the program lines LEI, LE2 and LE3 up to the point in time output A of the assembly ME, low potential can be seen immediately at i4 that after the setting process the next leading edge VE of the clock signal - Dia- even without the set command at input E 2, the multi-program line LT - is taken over by the master MA via whose unit the inputs El to E3 of the assembly ME gang SMA . By negation with logical 1 leads. Due to this fact, the help of the negation element N 2 is still set to the other one-memory element, even if the RMA of the master MA at the same time offers a high potential for setting the 1-signal required on its input tial, which is also accepted . So E 2 is no longer available

with at outputs QML and QM 2 of 35 to reset the memory element sen to desMasters MA after the lapse of the rising forward input Elan instead of logic 1 logic 0 gederflanke VE deep or high potential will be on exceeding. The signal voltage belonging to this is available for the slave SL on its inputs SSL of the diagram line LEI from time 1 4 to and RSL . The takeover takes place at time tS shown. After the point in time f 4, the following trailing edge of the clock signal leads. After 4 ° ren both inputs El and E2 of the assembly ME the course of the trailing edge RE of the clock signal to the high potential, which represents logic 0. From the point in time ti there is a majority decision at the output QS of the slave, there then results a changed signal configuration for the master MA with a low potential at input E3 of the module ME. A comparison with the signal form in takeover at the next leading edge VE of the diagram line LO shows immediately that the dynamic clock signal and a further takeover by mixed memory element after the change in potential at the slave SL at the following trailing edge RE of the output still remains clock signal still in reset state. After this trailing edge, the finding leads. In the meantime, until the transition QS of the slave SL reaches low potential, which corresponds to the time ti but also the other outputs of logic 0, see diagram of the two signal voltages on the inputs El and 50 lines LE3 and LO at time i41. E 2 is thus changed without a change in value, namely the memory element is reset and the potential that was originally high at input El and again at the state at time to at input E 2 is low. This corresponds to how far it is.

in front of logic 1 or logic 0. On the circuit shown in FIG. 3 shows a preferred one

Operation and mode of operation can be clearly seen that 55 embodiment of the assembly ME to the formation

the logical value of the output signal is based on a majority decision with signal inversion,

gang QS of the slave SL does not change, even if an essential part of this circuit is one

Resistance matrix alternating between high and low potential with resistors 1 to 3, the

Signal is output. Since in the event of a defect, the inputs El to E3 only represent the same time,

still constant low or high potential output 60 and a resistor 4. The more inputs El bis

a malfunction can be easily recognized. E3 lead high potential, the bigger a is

Until the time t2 , the fixed current through the resistor 4, whose voltage gestent logic state, does not change anything. After the time drop is used to control a transistor 5. Punkti2 changes the switching path of this transistor 5 fed to input E 2 via a signal from logic 0 to logic 1. This is the same as 65 working resistance 6 at terminals 7 and 8 for synonymous with the set command for the memory element. constant power supply. The output of this building- The majority of the inputs El to E3 of the building group is as in the arrangement according to FIG. 1 with A group ME supplied signal voltages has designated at. The switching threshold of the transistor 5 is

placed in such a way that this is just blocked at two low and one high potential at the inputs E1 to E3 , but is already switched through at two high and one low input potential. In this way, a signal is produced at output A which, because of the inversion by the transistor, is inverse to the majority of the input signals.

The arrangement according to FIG. 4 shows two memory elements SPG1 and SPG2, which are combined to form a memory module. The inputs of the one storage element SPG1 are designated E10, E 20 and £ 30; the clock signals are fed via the input T1 . The same applies analogously to the second memory element SPG 2, in which the inputs are labeled EU, E21 and £ 31 as well as Γ2. It is essential for this memory module that equivalent inputs E 10 and EU or £ 20 and E21 are fed with complementary signal voltages when operated correctly. This also results in signal equivalence for inputs £ 30 and E31. The same applies to the two equivalent outputs QS1 and QS 2, which also carry complementary signals when operated correctly. A monitoring device U is provided which continuously monitors the non-equivalence of the signals at the two outputs OS1 and OS 2 and immediately detects and reports a deviation from the signal equivalence regardless of the memory status and data flow.

This two-channel memory module including the device U monitoring the signal equivalence at the outputs QS1 and QS2 is advantageously designed as an integrated circuit, where it is essential that for each memory element SPG '. or SPG 2, the clock signals are still supplied via separate lines. In the case of these clock signals, it is assumed that under no circumstances can they fail at the same time as a result of a fault. However, if this requirement is not guaranteed in a switching mechanism, complementary clock signals are advantageously used, for example two square-wave voltages phase-shifted by 180 °. For one of the two inputs Tl and Γ 2 of the storage elements or 5PGl SPG 2 is then also provided an additional negation member. Such a measure leads to equivalent signals if both clock signals aiii fail at the same time in the lines to the inputs Tl and Γ 2 of the relevant memory module, so that at the same time there is signal equivalence at the outputs QSl and QS 2 , which is detected by the monitoring device U and reported as an error .

The use of the memory element according to FIG. 1 should not be restricted to an arrangement according to FIG. The memory element described works like an oscillator, the frequency of which is fixed externally by the clock signals. The phase position of the output signal voltage can be adjusted by influencing the inputs El and E2. The two possible phase positions can therefore be specified in any order - based on a time grid. The circuit can thus advantageously also be used as a modulator, for example.

1 sheet of drawings

COPY 209 544/497

Claims (4)

1 2 when the processing process of the digital Si patent claims runs: signals during a predetermined period of time, and those at the outputs of the relevant switching mechanism 1. Electronic storage element for digitally output signals are not only dependent on the data processing systems with high error 5 pending signals at the inputs of the switching safety, especially for the Eisenbahnsiche- works, but also on those management systems for processing binary switching signals that were created in the form of square-wave signals in earlier processing steps. The result is that for a switching voltage of a given repetition frequency using digital data processing, it is not only necessary to use an i? 5 master-slave flip-flop with a number of different logic elements on a key gate for the slave, but also memory modules. A indicates that the S input (SMA) is an integral part of such Schaltungskomdes Masters (MA) directly and its ^ input plexes are therefore flip-flops, which in the under- (RMA) via a negation element (N 2) to a wide variety of embodiments Use of majority decision-making with signal inversion. The subassembly (ME) is connected, which has three inputs (El, E2, E 3), especially in the area of railway security, of which switching technology and, for example, also with the reactor two (El, E2) for the binary switching variables in control are required, Particularly high safety requirements are placed on the shape of rectangular signal voltages, the logical values of which are specified by ao den, so that a data processing phase difference of 180 ° is guaranteed over a longer period of time, during which none are operational, and the third input (E 3) with that dangerous error occur. The requirement for the output (QS) of the slave (5L) is connected, the reduction in size and cheaper while remaining the same is assigned to the S inputs, and that the quality of the circuit systems used, following the clock signal required for triggering, is doubled on the market for electronic circuit panels given repetition frequency of the square-wave systems without magnetic circles, so that it has shaped signal voltages, whereby the reverse technology or wage-intensive magnetic ring core technology coincide with the edges of the signal voltages, for example on a spatially complex relay edge (RE) of the clock signal. can be dispensed with. These commercially available switching 2. Electronic storage element according to circuit systems are, however, not taken into account spoke 1 for a two-channel switchgear with high safety requirements on the top of each other complementary signals designed for the two named special fields. Channels, characterized in that for some years now, monolithic switching Memory chip developed from two identical memory circuits that are opposed to circuits dem (SPG1, SPG2) is constructed, whose equal- 35 discrete components by particularly high valuable inputs (£: i0 / £ ll, £; 20 / £: 21, £ 30 / £ 31) Reliability, high packing density, high switching when operated correctly, with complementary speed and low costs. Signal voltages are fed, and at the end of which the German Auslegeschrift 1 537 379 is a equivalent outputs (QSl, QS 2) a safety circuit that can be integrated into the Si to carry out Signal antivalence monitoring device (17) an- 40 known logical links that have a high closed is. , Guaranteed failure safety without the individual 3. Electronic storage element according to logic elements according to the fail-safe principle spoke up 2, characterized in that must be built for. In this safety circuit, two storage elements (SPGl, SPG2) are antivalent, each logic module has two-channel output clock signals in the form of 180 ° phase-shifted, whereby the two channels are provided with properly shifted square-wave voltages, system operation signals of complementary switching variables of which one clock signal leads directly and the ren. The non-equivalence is monitored independently of the data flow by an additional negation element. is led. With this safety circuit to carry out 4. Electronic memory element according to analog 50 logical connections, a system talk 2 or 3 is missing so far, characterized in that the right memory module, which is also a two-channel dual-channel memory module (SPGlISPG2) is built in, and also with complementary circuitry that monitors the signal antivalence. variable in the form of rectangular signal spand device (U) works as an integrated circuit recesses of a given repetition frequency,
is led. 55 The invention is based on the knowledge that it is particularly advantageous of the many known Flip-flop circuits that of the ÄS master-slave Flip-flops as the basis for the development of the system-compatible two-channel memory module The invention relates to an electronic memory 60 required electronic memory element to be select a link for digital data processing systems. The basic circuit of an ÄS master-slave high level of error security, especially for the iron flip-flops, is in Karl Reiss' book, »Integrated railway safety system, for processing binary digital components «- Small internship at Siemens Switching variables in the form of rectangular signal Aktiengesellschaft, Berlin / Munich 1970, p. 97 and voltages of a given repetition frequency are described in more detail under 65 98 and 344 and 345. Turning an i? 5 master-slave flip-flop with a flip-flop of this type usually consists of Clock negator for the slave. Modern derailleurs of the two normal i? 5 flip-flops, one of which is the digital computing work in steps. Da-Master, on the output side with the two inputs of the