DE2313186B2 - Circuit arrangement for entering binary information into a digital data processing system, in particular for railway safety - Google Patents

Description

S. R. QlO QtI

L. O O O L. L. O L. O L. L. L. O O L. O

S. R. QtQ 0 L. 0 0 L. L. L. 0 L. 0 L. L. 0 0 0 L.

35

is sufficient, characterized in that each of the two input terminals (KPL, KPO) of the changeover contact (SR) is constantly supplied with the signal corresponding to one of the two values of the binary switching variables and that the changeover contact (SR) üuc-r ci.i negation element ( NG 1) is connected to an input ^) of the memory element (5Pl) and the other input (R) of the memory element (SP \) is at constant low potential and thereby alternately receives one or the other value of the switching variable.

2. Circuit arrangement according to claim 1, characterized in that a Schwellwertüberwachcr (SWR 1) is connected to the input (5) of the switching contact (SR) downstream storage element (SP 1) via a diode (D 1), the second terminal of which is high Potential (H-) lies.

3. Circuit arrangement for the optional switching through of dynamic signals or for converting static signals into dynamic signals with the value 0 using a memory element with a master-SIave-Flipdop, with the one for the master a control part for a majority decision of two variables and the output signal of the slave is provided for the processing of binary Switching variables in the form of each rectangular, between high and low potential changing signals of a given repetition frequency, their binary values by a phase difference of 180 ° of the signal voltages are shown, the storage element of the truth table

45 is sufficient, as well as with a logic element on the basis of the majority sen.tschsidu.ng of three signals via a resistor circuit with two inputs for SchaUvarjable to be linked and an embossing input for a permanent signal corresponding to one or the other phase position of the switching variables to define the NAND or NOR function, characterized in that the dynamic or static signals (0 or L, H or T) are fed to both inputs (1) of the memory element (SP 2), that the two inputs (1) with one input of the logic element (NO) are connected, the second input of which is connected to the output (2) of the storage element (SP 2).

4. Circuit arrangement according to claim 3 for the transition to a two-channel circuit system with an original channel and a complementary channel, characterized in that d ;; S d ^: .c signals in the original channel via a negation element (NG 2) to a first memory element (SP 2) with a connected Logic element (NO) get into NOR function and that the said signals in the complementary channel are fed directly to a second memory element (SP 3), the NAND function being provided for the logic element (NA) assigned to this.

5. Circuit arrangement according to claim 4 for reporting the presence of static signals, characterized in that to the interconnected inputs (1) of the memory element (SP 2) in one channel and on the other hand to the output (3) of the memory element (SP 3) in the other Channel the series connection of a diode (D 2) with a threshold value monitor (SiV R 2) and another diode (D 3) is connected and that the threshold value monitor (SWR 2) is connected on the input and output side via a capacitor (C 2, C 3) is connected to ground.

The invention relates to a circuit arrangement for entering binary information into a digital data processing system, in particular for railway safety, each with an input terminal a changeover contact using a memory element with a master-slave flip-flop, in the one for the master a control unit for a decision making of two variables and the Auej.angssignal of the slave is provided for Processing of binary switching variables in the form of each rectangular, between high and low potential changing signals of a given repetition frequency, their binary values by a phase difference of 180 ° of the signal voltages are shown, with the storage structure of the truth table

S R QiO QlI

5o

L. 0 0 0 L. L. 0 L. 0 L. L. L.

0 0 L 0

enough. Herewith is the Boolean equation

QtI = S-R + QtO- (S + R)
Fulfills.

With modern information communication systems, ι, B. in railway safety technology, but also with the reactor control, switching mechanisms are required, whose links must work according to special safety principles, so over Data processing can be guaranteed for a long period of time in which there is no risk to the business Errors occur. Of the electronic circuit systems on the market

is denoted by SE. The clock signals required to control the two FUpflops MR and SE are fed directly to the master flip-flop MR via the terminal TE and to the slave flip-flop SE connected downstream via a negation element ND . The signal input into the AS master-slave flip-flop does not take place directly via the master MR, but via a control part BMG with three inputs connected upstream of the master MR. This assembly has the

A distinction is made between those who would give after io, a majority decision of the three

the fail-safe principle work and those that come from signals from inputs as well as an inversion

deviate from this principle, but in which one must be made. The control part is on the output side

Any errors that occur immediately and automatically are determined by BMG, on the one hand, directly with the master fiipfiop MR

will. This allows in the switching mechanism without timing and on the other hand via a further negation element

delay, a state can be set in which 15 ND 1 is connected to the other input of the master MR

there is no operational hazard. bound. When using a control unit BMG

Known is a safety circuit for through- without signal inversion, the two input leads of logic combinations (DT-AS 1 537 379), connections of the master MR compared to the present one guarantee a high level of error security without the representation being mixed up. The output Q of the individual logic elements after the entire memory element mentioned must be constructed using a feedback fail-safe principle. In this branch with one input tL.-s for the majority safety circuit, each link module decision provided control part BMG is designed as branching channels, whereby the two channels are linked. The remaining two inputs S and R for proper operation carry complementary signals Control part BMG are for switching variables. It is essential that the non-equivalence, which is monitored from square-wave signal voltages depending on the data flow, so that there are those that do not have a phase difference of 180 ° then security with regard to error detection, if Their logical values differ from the general switching state of the switching mechanism. To determine the respective logical one, an important feature of this safety value is a signal voltage - as will be explained later, furthermore, that as switching variable 30 with the aid of the diagram according to F i g. 2 explanatory square-wave voltages e given repetition frequency tert - two complementary rectangular amplitude and amplitude are used, whereby the two equal signals are used, which constantly have values of the switching variables against each other by a phase difference of 180 ° and differed from 180 °. As a result, their logical value is known through fixed assignment, probably on the original channels as well as on the grain size. The plementary channels of the switching mechanism described above in rough outlines regardless of the
Value of the respective switching variable on the relevant channel dynamic signals.

From the German Auslegeschrift 2 143 375 is a

Electronic memory element for digital data transfer 40 inputs S and R and an output Q and with

processing systems with a high level of fail-safety with a clock input TE shown,

knows that from its conception and structure Fig. 2 shows in several diagram lines the time

system-compatible in connection with the above curve of rectangular signal voltage

The safety circuit for implementation and the course of the clock signals for the terminal are located

gical links can be used. For a better 45 TE (Fig. 1). In the upper diagram line is the

Understanding is to be shown in the following with reference to Fig. 1, the timing of a clock pulse Γ,

to 4 the mentioned prior art with regard to the pulses of which are fed to the clock input TE

the electronic memory element as well as a in the. In each case · when there is a leading edge

Safety circuit i? M carrying out of logical comparison VE of the clock pulse T is the master flip-flop MR

links specified linkage closer se corresponding to d ^ r located at its inputs

consider: will. The figures show in detail the signal configuration set, it is and remains

Fig. 1 is blocked from a ftS master slave flip-flop with cias slave flip-flop SE . The master MR

memory element built up with an additional control part, output signals are

2 shows the temporally following trailing edge RE of a pulse of the clock profile of various signal voltages with assignment pulses T taken over in several diagram lines. During this takeover at a clock signal, the master, ViR, is blocked. The in the slide

Capable. 3 shows a circuit arrangement for a NAND gram lines PO and PL shown rectangular shape

or NOR element with signal linkage through multiple signal voltages are 180 ° against each other

decision and postponed in the phase and provide the two possible

F i g. 4 shows a truth table for the circuit arrangement, logical values 0 and L for the memory ^{arrangement according to FIG.} 3 when it is used as a member according to FIG. 1 used shadow variables as a NAND or NOR element. The second diagram line PO

F i g. 1 shows the known circuit arrangement thus shows the profile of that signal voltage which

of an electronic storage element for digital data corresponds to the value 0 of the switching variable, while

processing systems with high level of error security, the graph line PL shows the course of a signal span

schematic representation. This storage member shows the voltage in terms of their phase position

consists essentially of a KS master-slave value L to which the switching variable is assigned.

FliofloD. of which the master with MR and the slave To explain the mode of operation of the memory

Memory element is used to simplify the representation when dealing with exemplary embodiments the invention to be described only as a simple clock-controlled flip-flop with two

It is assumed that there is an input variable at input S , which is shown in the diagram line LS . The same applies analogously to the input R and the diagram line LR. The signal at the output Q of the storage element belonging to these two input signals can be seen from the diagram line LQ. In order to enable a comparison of the signal configurations with the truth table valid for the storage element, it is listed again below:

S. R QiO Qt \

L. 0 0 0 L. L. 0 L. 0 L. L. L. 0 0 L. 0

When comparing the diagram lines LS, LR and LQ with the diagram lines PO and PL , it can be determined that the input variables up to the point in time 1 0 at the input S of the memory element have the value L and at the input R the value 0, while the value of the output signal at Output Q is also 0. In the truth table, QtO denotes the "old" signal state at output Q of the memory element before the slave SE of the memory element took over the signal configuration present at inputs S and R of the control unit BMG. In each case on the trailing edge RE of the next following clock pulse, a value of the output signal applies to the output Q of the memory element, which value is generally designated Qt 1 in the truth table. From the diagram line LR it can be seen that after the time / 0 the input /? of the memory element present input variable changes its value from 0 to L, since the signal shown in the diagram line LR is now in phase with that which is shown in the diagram line PL . The values of this signal configuration can be found in the second line of the truth table with L, L and 0 for QtO. After the point in time / 1, the memory element outputs a square-wave signal with the value L at the output Q after a majority decision and acceptance by the slave SE. After the clock pulse between times / 1 and ti , the value of the signal at input 5 of the memory element has changed from L to 0, see diagram line LS and line three of the truth table. At time / 2, the result of the input variable change is still the value L at the output »2», as can be seen from the diagram line LQ ifl connection with the comparison signal m of the diagram line PL. The values 0.0 of the input variables specified in the last line of the truth table for the inputs S and R of the memory element with the value L at output Q are available after the trailing edge of the clock pulse between times ti and i3, because the value of the input signal at the input /? has changed, see diagram limLJ ?. As a result of this signal configuration, the slave SE emits an output signal with the value 0 after the takeover at time / 3.

In practice, two storage elements are combined to form a module for a two-channel Circuit arrangement, with similar inputs and outputs when working properly lead antivalcntc signals. The aul dem so ge Create original or complete Iu channel existing signals are created by additional drive Hung at each of these twin building citii; on anti valence checked.

A circuit system does not only consist of: Memory links, but also requires nocl different linking links. The üius der Aus Legcschrift I 537 379 known security circuit

ίο to carry out logical operations there are some Circuit arrangement, which is also nuf the Rasi of majority voting works. The circuit arrangement according to FIG. 3 shows in i'creinfachle Darstcllungswcisc this known circuit

is channeled. This essentially consists of a transistor TR, whose collector lii |! G; t via an operating resistance to positive potential. A resistor network with three ends E 1 is connected to the base electrode of this transistor TE

to El and EP. The inputs El and El ditser resistance matrix «ind for input variables to be linked in the form of rectangular signals, corresponding to one of the other rectangular signals of the diagram line PO oi; l <; r PL after

2. The input EP is referred to as the embossing input, because this input is always a comparison signal PO or the other comparison signal PZ. receives. In the first case, the circuit arrangement works according to FIG . 3 as a NAND element, in the wide case, the circuit arrangement has the function of a; NOR member.

In the truth table according to FIG. 4, the names express, El and EP iiirid the three Ii.iugänge de "logic element according to FIG. 3 as well as the for the output reference character A shown Furthermore, assuming that diiis' gate with the Vcrgleichssignal 0 a transition in Präpecin EP as NAND gate works (symbol in Fig. 3 top right), taking into account various

Combinations of input variables in the form of rectangular signal voltages entered the expected link results. If the inputs E1, E2 and EP after the second line of the truth table in FIG. 4 receive signals which correspond to the values 0, L or 0, the output A carries a rectangular signal with the value L. For better understanding, there are Te I of the truth table (line two, FIG. 4) shows the signal curves in the diagram lines LEI, LEI, LP and LA .mterhalb the dash-dotted line of F i; <. 2 recorded. Since the signal curves shown in this diagram line have a fixed temporal correlation with the comparison signals PO and PL , the value of the line shown in diagram line LE 1 can be used

Signals immediately indicated with 0 because the signal curves in the diagram lines LE I and PO are in phase. With a corresponding consideration of the signal course in the diagram line LEI it is found that the represented by this Signalverla Mt

The controlled variable has the value L. Accordingly, the signal curves in the diagram lines LP and LA represent the value 0 and L. The values of the input variables for the inputs El mivd El of the circuit arrangement according to FIG. 3 as well as the τ value of the

Signals at the embossing input EP when the circuit arrangement according to FIG. 3 is used as a NOR element (symbol in FIG. 3, bottom right) are in the last four lines of the truth table according to FIG . 4 entered

616

7 8

| en. The relationship is more logical after the preceding safety circuit for performing

The following explanations are easily understandable. Shortcuts as well as the well-known electrical

In the German Auslegeschrift 1 537 379, which niche storage element for digital data processing

the safety circuit for implementing logic systems with a high level of fail-safe operation is

Links are concerned, are still two-channel 5 voltage-appropriate working of the switching elements mentioned

Logic modules are described that consist of two always dynamic signals from one to the next

There are logic elements according to FIG. 3, whose switching element is passed on. With two-channel

Embossed complementary signals received. The output signals of the modules are in this order

In this way, each link module also provides complementary to each other, such as

two link elements an original and an io was already briefly explained above. It is easy to

Complementary channel. see a saving or linking

The invention is based on the switching element described above as a result of a defect in the output circuit

known devices for one or two-channel no longer outputs a square-wave signal, so that

Linking and storage of switching variables instead either constant low or high po-

in the form of rectangular signal voltages from, 15 is potentially present.

the binary values of which are distinguished by a phase difference. In the case of defects of this type, it is desirable that they differ from 180 °. On the basis of the system-known circuits instead of the high or low potential, the invention is based on the own variable with the value O, i.e. a dynamic one, to complete a rectangular signal that is output,
like logic and memory elements ao using a memory element with a built-in circuit system converter circuits to master-slave flip-flops, which create the above-mentioned, in which using the known truth table is sufficient for the processing of logic and memory elements for square-wave binary switching variables in the form of square-wave signals in the event of a defect in the converter-switched signals of a given repetition frequency whose output no binary value L is output as logical values due to a phase difference of ben. 180 ° of the signal voltages are shown as well

In one embodiment, a fuse using a link for the-

technically correct information input using the same signals as the truth table according to FIG. 4th

A L-r.switching contact can be realized, whereby the one is sufficient, the task becomes with regard to the second one

Bounce influence no falsification of the entered embodiment according to the invention solved by

Trigger signal. Furthermore, the information should be sent to both dynamic and static signals

Entry should be made in accordance with the system in terms of time. Inputs of the memory element are performed that the

With another embodiment, dynamic two inputs are to be connected to one input of the linking

mix signals independent of their phase position are connected to fung member whose second input

the comparison signals, that is, independently of each 35, is connected to the output of the memory element.

represented value 0 or I. switched through and depending on whether the logic element is in this

static signals in dynamic with the binary value 0 circuit arrangement for! optional through-connection

implemented. of dynamic signals or for converting

According to the invention, the task with regard to static signals is converted into dynamic signals as NAND

the first embodiment solved by the fact that each 40 element or NOR element works, gives this circuit

the two input terminals of the changeover contact arrangement in the presence of static Si

the signal corresponding to one of the two values of the signals either dynamic 0 or dynamic

binary switching variables is constantly fed and that L signal off. Becomes the link through

the changeover contact via a negation element with appropriate sound at the embossing input EF

is connected to an input of the memory element and 45 in FIG. 3 with the comparison signal of the value L as

the other input of the storage element is operated on a constant NOR element, so static high and

system lies at a low potential and thus alternately also low input signals exclusively in a dynamic

the one or the other value of the switching variable mixed signal of the value 0 converted,

receives. To form an original and an associated

With the help of this converter circuit for binary 50 complementary channels with antivalent dynamic

formations in digital data processing systems

is advantageously a further system-compatible switching through of dynamic signals or to

Building block created that meets the high security requirements, converting static signals into dynamic

Changes in particular in the field of iron signals in an advantageous manner after a further training

Railway safety technology is sufficient for the invention to be used in such a way that

Taking into account the switching times of one of the signals in the original channel via a negation link

in the other position of the changeover contact can be connected to a first storage device

advantageously an additional circuit to the logic element in NOR function get tau

Monitoring the position of the changeover contact to ensure that the signals mentioned in the complementary channel

going, whether one or the other end position has been reached, 60 are led directly to a second storage element

are provided. Such a monitoring where for this associated link

circuit, the NAND function is provided according to an advantageous development

of the invention with little effort dadurrh reali- If it is desired to check whether an original

be siert that at the input of the switching channel output dynamic signal of the value

contact downstream memory element via a 65 on Grand a corresponding input of a dyna

Diode a threshold monitor is connected, mix or static signals originate, i

its second connection at high potential is advantageous in a further embodiment of the invention

Both with the links of the confessing way to report the presence of static «

616

Input signals to the circuit arrangement for the optional switching through of dynamic signals © for converting static signals into dynamic ones Signals in an advantageous manner to the interconnected inputs of the memory element in one channel and on the other hand to the output of the memory element in the other channel, the series connection a diode with a threshold monitor and another diode be connected, whereby the threshold monitor is connected to ground on the input and output side via a capacitor each.

A transistor amplifier can also be provided here as the threshold value monitor The power supply comes from the circuit to be monitored. These transistor amplifiers can match those Form a series circuit on the input and output side, which in the two-channel structure of the known Memory and logic elements are provided for non-equivalence control.

Exemplary embodiments of the invention are shown in the drawing and are described in more detail below explained.

The figures show in detail

F i g. 5 shows a circuit arrangement for entering binary information via a changeover contact in a data processing system,

F i g. 6 a compilation of the values of various signals at the inputs and outputs of the Input circuit taking into account different operating states of the switch or with a Disturbance,

F i g. 7 shows a circuit arrangement for the optional switching through of dynamic signals or for Conversion of static signals into dynamic signals for two-channel operation with complementary ones Output signals and

8 shows a compilation of values for dynamic and static signals at different measuring points the circuit arrangement according to FIG. 7th

In the circuit arrangement according to FIG. 5 is a changeover contact 5 /? A negation element NG 1 is connected to the S input of a memory element SP 1 (according to FIG. 1). The / «input of this storage element SP 1 is connected to ground. When the changeover switch SR is in the illustrated position 5Rl, it is connected to the input terminal KPL , which carries the comparison signal of the value logic L in the form of a square-wave voltage, see diagram line PL in FIG. 2. The other input terminal KPO constantly receives the other comparison signal with the value Q, the course of which is shown in the diagram line PO in FIG. 2 is shown. A monitoring circuit Vl is connected to the output of the negation element NGl , which essentially consists of a threshold switch SWRi , which is connected to the negation element NG 1 via a diode Dl and on the other hand at a constant positive potential of the terminal Kl .

To understand the present circuit arrangement, it is particularly important to know how the ytändig existing on Λ input of the memory element 5PL deep potential in terms of the materials used as switching variable wave voltages impacts When comparing the two waveforms in the graph lines PO and PL to F ί g . 2 it can be seen that due to the phase shift by 180 ° of the two square-wave signal voltages, these alternately have low potential. Thus, the Λ input of the memory element 5Pl automatically alternately receives the one and the other value of the switching variable. This fact is evident in the compilation of FIG. 6 in the individual positions I to IV taken into account that under

the reference character R of the corresponding input of the memory element SP 1 for temporally successive half-periods of the square-wave voltages, alternating logical values L, 0 and L are indicated. The one in brackets after the value in front of

The letter T seen is intended to indicate the low potential at the input R of the storage element SP 1.

As long as the changeover switch SR is in the position SR 1, the negation element NG 1 receives an L signal from the input terminal KPL. This he

'S of the memory member SP appears on the 5-input inverted 1 as the O signal, cf. The first column under the reference numeral 5 in FIG. 6. Assuming that the output Q of the storage element SP 1 when taking the switches dividing the Umschal shown -

ao ters5Ä has an output signal with the generally designated value Q0, this value is retained as the value Q0 after the input signal configuration has been assessed and accepted by the slave SE (FIG. 1). In the subsequent half-period of

The signal voltages carry both inputs 5 and R of the storage element 5Pl O signal; the output Q carries a signal with the value Q 0. After the storage has taken place, this signal configuration is carried out taking into account the one specified for the memory element

Truth table for an output signal, see column QtX, with the value 0. As long as the position of the switch SR does not deviate from the one shown, the memory unit 5P1 sends the dynamic O signal to a data processing unit via its output Q

system DV.

In the table according to Fi g. 6 under II values are compiled which get for the case that the changeover switch SÄ is in a middle position between 5RI and SR 2 . The origin of the ne-

gation link NG 1 constantly at low potential, so that the 5 input of the memory element SP 1 is constantly at high potential after inversion. As already for the K input of the storage element 5P1 with regard to the constantly existing deep po-

potential was explained on the basis of the diagram lines PO and PL in Fig. 2, the 5-input of the memory element 5Pl receives in the considered operating state in an analogous manner when considering temporally successive half-periods of the signal voltage

Gen signals with the value 0, L or 0. These values are listed in the first column of FIG. 6 under the reference number 5 and position, in each case in brackets with an H as an indication of the constant high potential. As can be seen from the table, with the assumed middle position of the switch SR, the value of the output signal from the outputs of the storage element SPI does not change.

signal at output Q is therefore retained. this fact is particularly important with regard to bouncing processes of the changeover switch, since an apparently « Multiple entry of information at Prellvoigän gen cannot affect. Also, no change of information can be simulated by a bouncing process.

When the changeover switch SR changes from the middle position discussed to the position 5Ä 2, dei

616

<f

11 12

Negator NG 1 the dynamic 0 signal, which is listed according to logical values for the case that the Ne inversion at the S input of the storage element SPi gator NGi from the input of the SpeicnerglicdeSi SP t is present as an L signal. Regardless of which one is demolished. Then both inputs S and R value carry the output signal of the output Q at the following constant low potential which, taking into account the first observation point, has at the diagram lines PO and PL in FIG. 2 in both inputs S and R of the memory element SP 1, the two cases lead as a constantly changing logical value L signal - see first line of position III is processed into a dynamic signal, In FIG. 6 -, the output Q after multi-column Qt 1 of position IV is a consequence of a constant unity decision and acceptance by the slave SE change between an L and O signal at the output (Fig. 1) an output signal with the value L from. Recognize the io. However, this means under consideration of the table of values to be taken into account: shows clearly, placement of the comparison signals in the diagram line, that this logical value with unchanged position PO and PL of Fig. 2 that the output Q of the Speides switch SR is retained, see also column cher member SP 1 leads permanently low potential.
Qt 1 under item III, FIG. 6. The circuit arrangement according to FIG. 7 is used for

If the changeover switch SR does not immediately remain in position SR 'X as a result of a bounce pre- 15 optional switching through of single-channel output, but rather dynamic signals, for example due to the briefly being in the open state again, memory element SP 1 applies via its output Q, into one of the items under item II in FIG. 6 erected of values digital data processing system table under decomposition, after which the by only Tcurzzeitiges inputs of the signals feeding channel into a Originehmen the position SR 2 given signal state at "° nalkanal and a complementary channel for antiva output Q with Qt ί - QO - L is retained. lent rectangular signals. Furthermore, the switching

A corresponding mechanical construction arrangement according to FIG. 7 for converting the station of the switch SR , it is usually guaranteed signals, i.e. of high or low permanent power, that this is either in the position SR 1 or potential, in a dynamic 0 signal in the orifeinal position in the other position SR 2 , and that the Um- »5 channel with the output Al and in a dynamic switching times are low and therefore negligible. L signal in the complementary channel with the output For safety reasons, however, it must be assumed Ä ~ \. The circuit arrangement via the input E are that the changeover switch SR as a result of dismantling the signals supplied to access indirectly by a Nefektes in the central position can remain or that gationsglied NCl simultaneously to both inputs of the NOT gate NG \ of the switch SR off 30 of a storage member SP 2 and also tears immediately. In this case, as has been explained in detail on both inputs of a second memory element SP 3, the output by the memory element 5Pl remains. The two memory elements SP 2 and SP 3 correspond to the default state. Now, if this Signalzu- that in the circuit of Fig. 1 stand of the storage member SP 1 due to the preceded for the processing of the rectangular signal departed position of the switch a voltage dangerous 35, the values of which was located assigned by a phase operation condition, it will differ under the difference of 180 °. This presupposed malfunction should continue to be reported to the data processing facility DV and cannot enter the data processing system. that in the circuits explained are converted from a signal that corresponds to the harmless single amplitude? Lease no conclusions corresponds to operating condition. In order to recognize such situations 4 ° to the respective value of a signal in good time, the monitoring device is provided, that is, to determine the respective value U 1, which in the case of a dynamic signal with one or the other comparison signal of the diagram, the value L or 0 at the input S of the memory element line PO or PL according to FIG. 2 used SPl in connection with the additionally supplied must.

positive potential via the terminal K 1 to 45 properly in the original channel with the output A 1 is detected at the voltage just condition and SP1 outputs an output of the memory member diesbezüg- a NOR gate anliches signal over line Ll. The connection, the second input of which with the two capacitors C1 is dimensioned in such a way that the storage element SP 2 is connected during the Um inputs. Switching pauses of about 100 ms of the switch SR In the complementary channel, the storage element SP "is followed by a sufficiently high energy to supply the 5 ° a NAND element NA , whose second threshold switch SWR 1 is available, so input with the two inputs of the storage element during this No switching pauses any of the SP 3 is connected.
Error message is output via line Ll. The two inputs of the memory element SP 2 im

With a permanent central position of the switch SR original channel, the output between the positions SRI and SR 2 or with a 55 of the storage element SP 3 hn complementary channel is an interruption between the switch SR and the other input of a monitoring in the negation gited NGl gives the negator NGl Kon- direction V 2 connected, which monitors whether static stant high potential. After charging the Kon- or dynamic signals are supplied. In the wedensatorsCl there is the monitoring circuit U1 supply inputs of the threshold switch STFRl no 6c from a threshold monitor SiFÄ2, the independent potential difference more, so that over the line Ll depending on whether the necessary error message is issued when working properly. the memory element SP 2 in the original channel dynamic The error message can be supplied, for example, in the absence of 0 or L signals, via which output line L2 outputs a signal when the condition is correct. For example, test pulses exist. The diode D 1 has the effect that the 65 can, as in the circuit arrangement according to FIG. 5 capacitor C1 can only be discharged via the threshold switch of the threshold monitor SWR 1 considered above. SWR 1 consist of a transistor amplifier, des-

Under item IV of the table of FIG. 6 are sen power supply via the two diodes D 2 and

D 3 takes place, the capacitors C1 and C3 compensating for operational pauses in the power supply given by the dynamic signals. Both the NOR gate NO and the NAND gate NA consist of a circuit arrangement according to Fig. 3 with an embossing input EP, which in the case of the NOR gate continuously, the comparison signal having the value L and the achievement of the NAND function, the comparison signal 0 obtained, see diagram lines PL and PO in FIG. 2.

The mode of operation of the circuit arrangement according to FIG. 7 will be explained below with reference to FIG. 8 designated table explained in more detail. In the first column reference numerals are listed, which are used in the circuit arrangement according to FIG. 7 were used, among other things, to designate measuring points. Depending on the signal at input E, the signals or signal states to be achieved as a result are listed in the following columns. The circuit arrangement according to FIG. 7 is normally with its input E to the output Q da memory element SP 1 according to FIG. 5 connected. Taking into account the column α in FIG. 8 it is assumed that the memory element SP 1 outputs a constant high potential H, that is to say a static signal, via its output Q due to a defect. This signal is inverted by the negation element NG 2 and appears at the two inputs 1 of the memory element SP 2 as a low potential T. This is processed by the memory element SP 2 so that a high static potential H arises at its output 2, which is the one input of the NOR element NO is supplied. This logic element simultaneously receives a low potential T via its other input. As a result, output A 1 emits a dynamic signal with the value O. Accordingly, in the complementary channel at the output ^! of the NAND element NA a dynamic signal with the value L can be expected. This comes about in such a way that the high potential H at the input E is converted by the storage element SP 3 into a low static potential T which is applied to one input of the NAND element NA . The other input of the NAND element NA receives the high constant potential H. This signal configuration leads to a dynamic signal with the value L, taking into account the comparison signal with the value O at the embossing input EP , taking into account the accuracy decision (see FIGS. 3, 4) When determining the output signals of the two link elements NO and NA when purely static signals are present at other inputs, the table according to FIG. 4 can also be used. Lines two and three apply to the NAND element in this context, with the static signals at the inputs of the NAND element NA apparently due to a continuous switchover of the signal values occurring after every half cycle. Correspondingly, NO applies to the NOR element if the Lines two and three from the bottom of the table according to FIG. 4 can be applied.

A defect in the memory SP Ί in the circuit arrangement according to FIG. 5 can also have the effect that at the output Q and thus at the input E of the circuit arrangement according to FIG. 7 is low potential, which is indicated by the letter T in column b of Fi g. 8 indicated st. As can be seen from the table, this disorder ultimately also has the consequence that there; Output signal in the original channel at output A 1 d; is narnish and has the value O, while the dynamic L -'- signal is present at the output ig / Π of the complementary channel.

In the two cases of malfunction assumed above, i.e. constantly high or low; s potential at input E, the monitoring circuit receives i / 2 (FIG. 7) at both inputs - see reference numerals 1 and 3 as well as the first column in FIG. 8 with the associated values in the columns α and b - zveimal exclusively low potential T or exclusively high potential H. Thus, the power supply of the threshold value monitor SWR 2 is in each case below a predetermined threshold, so that as a sign of a disturbance above d; .e Line L 2 no more test pulses are output.

In the last two columns c and d of FIG. 8, it has been assumed for input E that this receives a dynamic signal with the value O or L from the memory element 5Pl (FIG. 5) when the circuit arrangement is working properly. In both cases the output A 1 of the original channel and the output / TI of the complementary channel carry a dynamic signal with the value O or L. The output signals are complementary to each other.

The description of the mode of operation of the exemplary embodiment according to FIG. 7 has shown that this Circuit arrangement in an advantageous manner on the one hand for switching through dynamic signals and on the other hand, it is also used to convert static signals into a dynamic O signal in the original channel can be used.

For this purpose 4 sheets of drawings

Claims (1)

Patent claims: 1, circuit arrangement for entering binary Information in a digital data processing system, in particular for the railway • icbering system, each using an input terminal of a changeover contact a memory element with a master-slave flip-flop, in the one for the master a control part for a majority decision of two Variables and the output signal of the slave is provided for the processing of binary Switching variables in the form of rectangular, Signals of a given repetition frequency alternating between high and low potential, their binary values are represented by a phase difference of 180 ° in the signal voltages are, where the storage element of the truth table