DE1566782B1 - Procedure for testing pulse-operated circuits and circuit arrangements for its implementation - Google Patents

Description

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The invention relates to a method for testing. Advantageously, only one pulse is removed at a time.

of pulse-operated circuits in which the switched, so that in the event that a channel is faulty outside The value that lies within the specified limits is a brief interruption in the output range a measured variable is guaranteed by a static signal from the safety measuring system the other is left within the specified limits and no safety functions are triggered, However, the error can be detected according to the correct state. Range of values through a series of clock pulses The pulses for the pulse-operated circuit

is shown, which are generated in clocks and arrangement are expediently generated in a clock of switching elements as a function of which contains a pulse generator, which analog or static signal present measuring io a blocking stage, by means of which the pulses from size and / or from 'Linking elements are faded out, is connected downstream. A blocking stage is required for each channel in which the same measured variable is required, which is either transmitted by m different channels and, in the case of a common pulse generator or, advantageously, failure of the pulse series, is fed in at least η channels from a separate pulse generator each, triggering a safety function will. 15 so that the clock for a channel has both a

To such pulse-operated circuits contains a pulse generator as well as a locking stage, listen to the so-called safety measuring systems, such as. B. according to the German patent specification 1225 078, controlled. The distribution of the blocking signals to the blocking stages in the individual states at a measuring point is expediently represented by static signals 1 or 0, but rather 20 ring counter, the individual stages of which are each one blocking stage by means of a series of pulses that control when the is present. So that the measuring signal at the output of a circuit part is not switched to the ring counter with each clock pulse, the exits will be absent if they are absent. These impulses output impulses of the impulse generator are fed to logic elements which are fed to the disconnectors. The output of this reducer which is still fed with clock pulses and only 25 and the output of the ring counter stages emit an output signal when they are linked, so that only when their measurement signal coincides, the characteristic pulses and the clock output pulses close a blocking signal to the blocking stage at the same time available. The output is guided. So that the coaster can deliver unambiguous pulses as clock pulses for further, backward pulses of a defined shape, this is a connected linkage. There are 3 ° downstream pulse-shaping flip-flop stage, which also emits no pulse from one element, be it that it is still defective or that it is directly controlled by the pulse generator, or that one of the two is fed to it. In an advantageous embodiment, the impulse series fails, if the impulses of the ring counter are only switched on if those at the end of the chain are also off. Should the impulses be switched off in the designated channels only then not be given if two 35 were. For this purpose, the impulses are no longer delivered to the ring counter stages by triggering stages or by several chain links. A trigger stage is assigned to each ring output, so its outputs can be assigned to an OR counter stage. This who circuit will be linked. Furthermore, in the case of the same impulses of the impulse measuring system known at one input, the same measured variable is fed to the generator as the ring counter stage. Furthermore, with m signals transmitted in separate channels, 40 they receive pulses via a second input, each of which η signals can trigger a safety function from the output of the assigned blocking stage. Such a system will be necessary. Appropriately, those of the second one system are designated. Most of the time, a 2 out of 3 system gear fed impulses is out of phase with the first gear fed impulses.

The invention is based on the object of continuously checking a channel by means of the pulse-operated circuit mentioned at the outset, with which the ring counter can be checked in a bezu without a safety radio position being able to be stopped. To tion is triggered, even if a functional check of the circuit arrangement can channel is faulty. According to the invention, this will be provided a further circuit which also achieves the object in that cyclical pulses of 50 contains a ring counter, which runs synchronously with the ring counter in each case n-1 pulse series switched off briefly in the actual test circuit. If the pulses fail to occur due to the outputs of corresponding stages in the two rings, there is an error in a channel whose pulses are not linked to one another in such a way that when they are switched, a fault message is given by a fast-switching counter at the different counter reading from the output of the pulse-operated circuit 55 will.

Signaling circuit an error is signaled. The series of impulses becomes just one at a time

The circuits for triggering the pulse functions are hidden, so this must signal the error on the other hand, so sluggish that they are checking the sender terminating element in the event of failure of a single one do not address. Your switching time must therefore respond with greater impulses. In an advantageous embodiment as the time in which the clock pulses are switched off 60 approximate form, the terminating element contains a transformer will. It should also be noted that in one with a core of preferably one material Cycle through all combinations of n — 1 channels with a rectangular hysteresis loop, which in the event of failure will run. It is often not necessary and a pulse is driven into saturation so that often not at all desirable that its output voltage disappears for a short time with each cycle. A impuls impulses can be switched off. There are 65 fast-switching devices connected downstream of the transformer Therefore, according to a further development of the invention, clock latching relay that is also purely electronic impulse can only be after a certain number of times, then indicates the error. Pulses switched off. On the basis of the drawing, in which an execution

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example, the following are the sets. The step-down circuit consists, for example, of the invention and other advantages and additions of two stages U ₁ and U ₂ , the outputs of which are described and explained in more detail in a. The execution NOR gate 15 are linked. The output chip example is used to test a 2v3 safety of the NOR gate 15 prepares a bistable system, which accordingly contains three subsystems, of 5 trigger stage B ₁ , so that these two can trigger a safety function when one of them arrives. Pulse from pulse generator T via line 6 It shows switched and switched on again with the next pulse.

F i g. 1 a clock for the security system is switched back. This control of the F i g. 2 the actual test circuit, bistable multivibrator, is achieved that the lower

3 shows a control circuit for the test circuit, despite pulses having a defined form and duration tion and the small pulse-pause ratio. These

F i g. 4 one of the test circuit adapted termination pulses are the inputs of the NOR gate 16, circuit. 17 and 18 supplied, the output signals via

In FIG. 1, which shows a clock generator for the first sub-lines 9 ', 9 " and 9'" of the blocking stages 8 of the clock system, a pulse generator is supplied with T.

The other input of this NOR gate is from

pulses from the clock generators of the second and third are each supplied to a stage R ₁ or R ₂ or R _{3 of} a ring counter subsystem. The output pulses controlled. Each of these ring counter stages is one of the pulse generator T, the frequency of which is assigned, for example, to the subsystem of the security system and amounts to 1 kHz. 13 "or 13 '". In case of failure clock of the second and third subsystem of a clock continue the ring counter is not passed more, on the other hand be connected with them two short, and it is an error is displayed, time stages Z ₁ and Z ₂ are driven, the the impulses of z. B. by means of control lights 19, 20 and 21, the pulse generator in short pulses of z. B. 30 μββΰ 25 amplifiers 22, 23 and 24 of the ring counter stages are switched duration with a small mark-to-space ratio. During normal operation, the convert lights. One short-term level Z ₂ is switched on directly, lamps on cyclically. An error manifests itself in one of the other controlled via a NOR gate 4, thus disturbing the cycle.

that their output pulses by 180 ° against each other The on lines 13 ', 13 "and 13'" are fed shifted, provided the pulse-pause ratio 30th pulses switch the ring counter only then, the generator pulses is one. The output pulses if their stages via lines 25 ', 25 "and 25'" of the NOR gate 4 are obtained via a further NOR enable signal. These release signals wer-gate 5, which is used for decoupling, and _{supplied via one of the flip-flops, ST 1} , K ₂ and K ₃ , from line 6 'of the circuit arrangement according to FIG. 2 to which each of a ring counter stage and a sub-system is assigned and there with the pulses of the clock generator of the 35 system and has two inputs, second and third sub-system mixed, which are obtained from one of them via the lines 13 'or the same way are supplied via lines 6 "and 13" or 13 '"from the corresponding clock generators 6'". The impulses thus generated on a line 6, the same impulses as the corresponding ring impulses, are therefore only fed to the counter stage, and of which the impulses fade when all three clock generators have failed. 40 other input via lines 14 ', 14 "and 14'" The output of the short-term stage Z ₂ is controlled via a NOR gate 7 with the stage 8, which is used for the output signal of the corresponding blocking phase rotation, and which is controlled by a series of pulses Input of a further acting as a blocking stage is formed, from which ren NOR gate 8 is connected at regular intervals, to which a power pulse is masked. As can be connected downstream in the description level. A second inducement of the clock according to FIG. 1 mentioned, the pulses emitted via a line 9 'via a line 9' to the lines 13 and 14 are phase-shifted from the switching shown in FIG. 2, are fed to the toggle arrangement. The output pulses of the stages K ₁ , K ₂ and K _{3 are switched} back and forth in time with the pulse generator blocking stage 8 or the downstream power stage.

are switched via two NOR gates 12 and 13 and via 50 2 illustrated actual blends described in more detail. By means of a borrowed test circuit supplied. The output pulses at terminal 26 reset pulse are fed to the short-term stage Z ₁ , the ring counter stages R ₁ , R ₂ and R _{3 are brought} to a further NOR gate 11 with a given position via a NOR gate 10 that, as in the Figure indicated, otherwise routed to a downstream power stage, 55 on the connection line between the stages R ₁ on the other hand via a NOR gate 12 to the test and R ₂ O signal, on the connecting lines interconnection according to FIG. 2. The numerous NOR gates see the stages i? ₂ and R ₃ and between the serve for decoupling and phase rotation. There is 1 signal at stages R ₃ and R _1. The next the locking level 8 can, for. B. limit indicator on pulse from the reduction stage CZ ₁ , U ₂ are closed, which switch through the pulses on logic 60 NOR gate 16 1 signal to the locking stage 8 of the members of the security system when the first subsystem. As a result, a pulse on the measured value falls within a set setpoint line 14 '. With an uninterrupted pulse train area. The output pulses of the gate 11 are the flip-flop K ₁ regularly over the line can serve as clock pulses for the logic elements 25 'enable signals to the ring counter stage R ₁ . 65 duration from the time interval between the impulses

The over the lines 6 ', 6 " and 6'" of the circuit of the line 13 'and those on the line 14' ne F i g. 2 supplied pulses are matched in one. In fact, the enable signals are reduction circuit z. B. in a ratio of 256: 1, but because of the switching time of the K ₁ flip-flop a little

shifted against the pulses on the line 13 ', so that when the counter stage is not enabled, they reach the counter stage input and cannot cause a switchover. If, however, a pulse on the line 14 'fails, the flip-flop K ₁ does not switch over until the S next but one pulse. As a result, the release signal is lengthened so that a pulse from line 13 'reaches the counter stage and can switch it over during the duration of the release signal. On the connection line to the counter stage R _{2 there} is thus a 1 signal, the counter stage R _{2 also} switches over, and at one input of the NOR gate 17 there is a 0 signal. At the next 0 signal pulse from the reducer, the NOR gate 17 sends a blocking signal to the blocking stage 8 of the second subsystem, so that a pulse is faded out from the output pulse series for the second subsystem, which in turn sends an extended release signal from the flip-flop K ₂ to the counter stage R. ₂ and the ring counter is switched on. A corresponding process is repeated when switching over the counter Fi level .R ₃ . : J |

With the help of three buttons t _± , t ₂ and i ₃ , the flip-flops can be held in such a switching state that the corresponding ring counter steps do not receive an enable signal and the ring counter is stopped.

To check the test circuit according to FIG. 2, the in F i g. 3 shown circuit arrangement may be provided. This contains a reduction circuit which is fed by the pulse generators T and which has the same reduction ratio as that in FIG. 2 illustrated coaster U ₁ , U ₂ has. The output pulses of the reducer control a ring counter with the stages R ₁ , R ₂ ' and R ₃ ' , which is connected to the ring counter according to FIG. 2 runs synchronously. Since the pulses on line 6, with which the coasters are controlled, and the pulses on lines 13, with which the ring counter of the test circuit is controlled, are out of phase with each other, the ring counter of the control circuit according to F i g. 3 a NOR gate 27 connected upstream. By means of a reset pulse simultaneously supplied to terminals 26 (FIG. 2) and 26 '(FIG. 3), the coasters and the ring counters can be brought into the same initial state. The signal on the connecting line between two stages of one counter is the input of a NOR gate 32 or 33 or 34, the corresponding signals of the other counter, which are inverted in NOR gates 29, 30 and 31, are the other Input of the NOR gate supplied so that if the status of one ring counter differs from that of the other, at least temporarily an error signal arrives at the input of a reporting unit ME , which displays the fault optically or acoustically.

In Fig. 4 is the circuit diagram of a termination circuit for a pulse-operated circuit which is adapted to the test circuit described. This terminating circuit has the task of generating a continuous DC voltage from the incoming pulses to create. If an impulse is missing in the regular sequence, i. i.e., is the time of one pulse to the next greater than a certain amount, the output voltage must disappear until the next impulse arrives.

The terminating circuit consists essentially of a bistable multivibrator K ₁ , to which the output pulses of the logic elements are fed and which controls a counteracting amplifier stage T ₁ , T ₂ with an output transformer U ₂ via a transformer U _1. The input pulses throw the bistable multivibrator X ₄ back and forth. As a result, the input transformer V _{1 of} the push-pull amplifier is magnetized back and forth, so that the two output amplifier transistors T ₁ and T ₂ are controlled. These magnetize the output transformer U ₂ back and forth, in the output winding of which a square-wave voltage is induced, which is rectified and a fast-switching, latching relay R is actuated.

If one or more pulses are missing, the input transformer U _{1 is} saturated, so that the two push-pull transistors no longer receive any control voltage and are blocked. This means that the output voltage disappears, the relay drops out and a fault message can be triggered. In addition to the fast-switching relay R , other relays are connected to the output of the terminating circuit which belong to a static logic circuit and which respond only when several pulses fail. If pulses fail in at least two subsystems, as is the case, for example, when a measured variable exceeds its predetermined measured value, the static logic circuit triggers control commands that regulate the status at the measuring location or shut down the system.

From the above description of the exemplary embodiment - or / and the features and instructions that can be taken from the associated drawing are, if not previously known, in detail, as well as their combinations with one another, disclosed here for the first time, as valuable inventive To see improvements.

Claims (18)

Patent claims: 1. Method for testing pulse-operated circuits in which the value range of a measured variable lying outside the specified limits is represented by a static signal, the other value range lying within the specified limits and corresponding to the correct state is represented by a series of clock pulses that are generated in clocks and are switched through by switching elements depending on the measured variable present as an analog or static signal and / or by logic elements in which the same measured variable is transmitted in m different channels and a safety function is triggered in at least «channels if the pulse series fails, characterized in that cyclically pulses of n - 1 pulse series are switched off for a short time and that if the pulses fail to occur due to an error in a channel, the pulses of which are not switched off, there is a fast switching circuit at the output of the pulse-operated circuit n the signaling circuit an error is signaled. 2. The method according to claim 1, characterized in that only after a certain Number of clock pulses pulses are switched off. 3. The method according to claim 1 or 2, characterized in that in each case in a channel only one clock pulse is switched off. 4. Circuit arrangement for performing the method according to one of claims 1 to 3, characterized in that a clock with a pulse generator (T) is provided, the pulses of which advance a ring counter whose individual stages (R ₁ , R ₂ , R ₃ ) each control a locking stage (8) connected downstream of the pulse generator (Γ) and thus cause pulses to be switched off. 5. Circuit arrangement according to claim 4, characterized in that the output of the pulse generator (T) is connected to the input of a reducer (CZ ₁ , CZ ₂ ) and that the output of the reducer (U ₁ , U ₂ ) and that of the ring counter stages CjR ₁ , R ₂ , R ₃ ) are linked to one another in such a way that a blocking signal can only be supplied to the blocking stage (8) assigned to the respective ring counter stage (R ₁ or R ₂ or R ₃ ) when their output pulses coincide. 6. Circuit arrangement according to claim 4 or 5, characterized in that the coaster (U ₁ , U ₀ ) delivers release signals to a pulse shaper flip-flop (B) which can be controlled by the pulses from the pulse generator (T). 7. Circuit arrangement according to one of claims 4 to 6, characterized in that the ring counter (R ₁ , R ₂ , R ₃ ) can only be switched further when pulses are switched off in the channels provided. 8. Circuit arrangement according to claim 7, characterized in that the release signals for the ring counter stages (R ₁ , R ₂ , R ₃ ) are supplied by flip-flops (K ₁ , K ₉ , K ₃ ) , each of which has a ring counter stage (R ₁ or R ₂ or jR ₃ ) are assigned and controlled via an input from the pulses supplied to the corresponding ring counter stage (R ₁ or R ₂ or R ₃ ) and via a second input from the output pulses of the pulse block (8) of the corresponding clock generator are. 9. Circuit arrangement according to claim 8, characterized in that the pulses fed to the ring counter stages (R ₁ , R ₂ , R ₃ ) are out of phase with the output pulses of the blocking stage (8). 10. Circuit arrangement according to claim 9, characterized in that the output pulses of the pulse generator (T) on the one hand a timing element (Z ₂ ), the pulses of a predetermined duration to the locking stage (8), which the associated flip-flop (K ₁ or K ₂ or . K ₃ ) and optionally other units of the pulse-operated circuit controls, outputs, on the other hand, via a delay element, in particular a NOR gate (4), the reducer (U ₁ , t / ") and a second timing element (Z ₁ ) are fed, which controls the associated ring counter stage (R ₁ , R ₂ , R ₃ ) and the associated trigger stage (K ₁ , K ₂ , K ₃ ) and possibly units of the pulse-operated circuit arrangement. 11. Circuit arrangement according to one of claims 4 to 10, characterized in that means for stopping the ring counter (R ₁ , R ₂ , R ₃ ) are provided in a certain position. 12. Circuit arrangement according to claim 11, characterized in that each flip-flop (JC ₁ , K ₂ , K ₃ ) is assigned a switch (t _v t ₂ , t ₃ ) , by means of which the flip-flops (K ₁ , K ₂ , K ₃ ) can be determined in such a position that the associated ring counter stages (R ₁ , R ₂ , R ₃ ) do not receive an enable signal. 13. Circuit arrangement according to one of claims 4 to 12, characterized in that each ring counter stage (A ₁ , R ₉ , R ₃ ) switches a control lamp (19, 20, 21). " 14. Circuit arrangement according to one of claims 4 to 13, characterized in that a further ring counter (A ₁ ', R ₂ , R ₃ ) is provided which has the same number of stages as the first ring counter (R ₁ , R ₂ , R ₃ ) and runs synchronously with this, and that the outputs of two ring counter stages (A ₁ , R ₁ or R ₂ , R ₂ ' or R ₃ , R ₃ ) are linked to one another in such a way that a fault message is issued when the count is different. 15. Circuit arrangement according to one of claims 3 to 14, characterized in that each channel is terminated by a unit that responds if a single pulse is lost. 16. Circuit arrangement according to claim 15, characterized in that the terminating unit contains a transformer (U ₁ ) with a core, preferably made of material with a rectangular hysteresis loop, which is saturated when a pulse fails, so that its output voltage disappears briefly. 17. Circuit arrangement according to claim 16, characterized in that the transmitter (U ₁ ) in the output of a controlled by the output pulses of the pulse-operated circuit bistable multivibrator (K ₄ ) and with its secondary winding controls a push-pull amplifier (T ₁ , T ₀ ) , whose Output voltage can be fed to a switching and display device. 18. Circuit arrangement according to one of claims 15 to 17, characterized in that the terminating unit is followed by a fast-switching, latching relay. 1 sheet of drawings COPY 009 541/174