DE2365092C3 - Electronic circuit for frequency and phase monitoring of clock pulses - Google Patents

Description

The invention relates to an electronic circuit according to the preamble of the patent claim 1.

When transmitting information, it is often necessary to have transmitting and receiving devices with a common Synchronize clock signal. The clock signal is often transmitted over long distances for this purpose, consequently, frequency and phase errors and ultimately errors in the transmission of information arise can.

This results in the need to check such a clock signal for frequency and phase errors monitor. The circuit for monitoring the clock signal must be designed to be fail-safe be that the clock signal in the event of a signal error in no case, i. H. even in the event of failure or errors of Components, to the output; the circuit can get. When using direct current signals, process Blocks is the risk of such a transfer of faulty clock signals particularly large. On the other hand, there is a risk of errors in AC signals via the input and output transformers processing blocks greatly reduced or even completely locked out.

A circuit arrangement is already known in which has a shift register consisting of several stages with an input terminal for the Receipt of the pulse series to be monitored and a clock pulse generator connected to the shift register with a higher pulse repetition frequency than that of the pulse series to be monitored for shifting of the pulses fed to the input terminal is present through the shift register and one on the one hand to the shift register and on the other hand to the alarm arrangement connected branching arrangement is present in response to the advancement of the monitored pulses of the alarm arrangement a signal alternating between two voltage levels with a higher repetition frequency than that Pulse repetition frequency of the pulse series to be monitored supplies (DE-OS 21 07 245).

Furthermore, a clock supply system is known in which each clock generation unit has one stage a bistable circuit is arranged, at whose outputs a clear criterion for the active State or the reserve state of a clock generation unit is available, in which still in Each clock generation unit has a signal generator which, on the one hand, has the outputs of the bistable Circuit is prepared and at its output the state of the relevant clock generation unit characterizing criterion is available in the form of a preparation signal and finally in the to be supplied clock receiving unit per clock phase an evaluation circuit is available, which both with the clock as well as the preparation signals of both clock generation units is applied and the only over the clock sent by the clock generation unit marked as the active unit Forwards clock amplifier stages to the individual clock gate inputs (DE-AS 20 59 797).

The invention is therefore based on the object of providing a fail-safe electronic circuit for frequency and to create phase monitoring that does not occur in the event of frequency and phase errors or errors in the Blocks in the circuit allows the clock signal to be passed on.

This object is achieved according to the invention by the measures specified in the claims .

The advantages of the circuit, in addition to the fail-safe nature of the circuit, are the particularly simple structure In contrast to other circuits, phase and frequency can be checked on a single channel and in the fact that the circuit only depends on a renewed acknowledgment signal after a recognized Clock signal error can be restarted. This means that there is an unwanted transmission of individual clock signals largely excluded without prior elimination of the present error.

An exemplary embodiment is described below with reference to the drawings.

F i g. I shows a block diagram of the circuit,

Fig. 2 shows the signal sequence of the clock monitoring with a perfect clock signal,

F i g. 3 shows the signal sequence when the pulse sequence is too long,

F i g. 4 shows the signal sequence when the pulse train is too short

ge of the beat,

F i g. 5 shows a signal sequence for clock monitoring in the case of a clock pulse train with a multiple of the normal working frequency.

To explain the circuit, the clock monitoring for normal operation, for a Clock pulse train that is too long for a clock pulse train, which is too short and described with a clock pulse train with a multiple of the normal working frequency.

1. Cycle monitoring during normal operation

The normal course of the clock is to be understood here when the clock pulse is within a prescribed time tolerance follows the previous clock pulse

According to Fig. 1 and Fig.2 an acknowledgment signal Q is first at the clock monitoring at short notice. It is assumed that the acknowledgment signal is generated by an executed also in a secure module art circuit such that by an error never a time-L-Q signal is applied This Qaittungssignal Q is a memory 5p with reset priority one hand directly and on the other hand, via the OR gates O \ and O ₂ supplied. This sets the memory Sp; Signal 2 persists. An applied acknowledgment signal Q leads the AND element U \ via the OR element O \ and via the memory Sp to the L signal at the same time. If a clock pulse is applied to U \ at the same time, the condition of the AND element U \ is fulfilled so that an L signal is carried at its output. The output signal 3 of the AND element U _{1 also} represents the output of the overall clock monitoring. The signal 3 is fed to the timer 71, whereby the signal 4 is set at its output for the time of the time delay 1 1 by the timer. The signal 4 is located at the AND gate U ₂ at the same time as the signal 7 is at this time to logic zero for the condition of the AND element Ui is given, and at the output to the signal 5 at the time delay T ₂ to . The signal 6 of the output of the time delay element T ₂ and the signal 5 are thus present at the UN D element U _3. The condition of the AND element U ₃ is thus not given as long as the signal 5 which initiates the time delay ti is still present. With the absence of the signal 5, the condition of the AND element U _{3 is} fulfilled, whereby the signal 7 is applied on the one hand to the OR element O \ and on the other hand to the AND element U ₂ . The presence of signal 1 at the AND element U ₂ ensures that no further signal can be passed through the AND element U _2. As a result, signal 5 remains at logic zero in any case, and the output of time delay element T ₂ , signal 6, is passed on as signal 7 via AND element U _3. The length of the signal 7 is thus determined exclusively from the length of the signal 6, reduced by the signal 5, at the output of the time delay element T ₂ . Via the OR element O ₁ , identical to the signal 7, the signal 8 is now again at the AND element U \. If a further clock pulse Tein occurs for the duration of the set signal 8, the condition of the AND element U \ is again fulfilled, since the memory Sp is still set. The storage position of the memory 5p is alternately maintained by the negated clock signal (T) M or the signal 8, both of which are fed to the input R of the Lt'memory via the OR element O _2. This process is repeated as long as the clock signal T falls exactly within the time interval <2 shown in signal 6. Thus, when the clock is running normally, the monitored clock signal Tan is present at the output A of the circuit.

2. Clock pulse train too long

According to Figures 3 and Fig. 1 follows at too long clock pulse sequence of the following on a first clock pulse clock pulse outside the described in item 1 time rZ by the absence of L-signal 6 at the output of time delay element T _2, the signal 7 at the output of AND gate U ₃ also to logic zero. As a result, the signal 8 at the output of the OR element O _{1 is set} to logic zero and each subsequent clock pulse no longer meets the condition of the AND element U \

By the absence of L-signal 8 at the output of the OR gate O _x of the memory Sp is the next clock pulse reset (output logical zero.) As a result, the circuit is also on Ausgar ^ A Taktsigna no! 7 "more; the clock monitoring must be restarted via the quilting signal Q.

3. Clock pulse train too short

If the clock pulse sequence is too short, it follows from FIG. 4 and FIG. 1 the subsequent clock pulse to the previous one already in the time interval 1 1 after signal 4.Because at this point in time the memory Sp is only held by the negated clock signal, it is unconditionally reset as a result of a clock signal T that now occurs AND element U \ no longer fulfilled. This means that no more clock pulse arrives at output A of the clock monitoring. As a result, the clock monitoring can only be started again via an acknowledgment signal ζ).

4. Clock pulse train with a multiple
the normal working frequency

According to FIG. 5 and FIG. 1, the first clock pulse with the acknowledgment signal Q reaches the AND element U ₁ , and the clock monitoring is triggered as in the normal sequence according to FIG. The next clock pulse, on the other hand, lies in the time interval M after signal 4 in accordance with FIG.

However, this means that signal 7 at the output of AND element U ₃ and also signal 8 at the output of OR element O \ are definitely set to logic zero. This means that the condition of the AND element U \ is not given, and the clock cannot be passed on to the time delay element T ₁ . On the other hand, if there is no L signal 8 and if the signal Γ is present via the OR gate O _2, the memory Sp must definitely be reset, since its input is set. As a result, the condition of the AND element U \ is no longer fulfilled for a! H subsequent pulse pulses. The clock monitoring can therefore only be started with a new acknowledgment signal P.

Technical design

In the technical implementation, the clock monitoring circuit must are created from fail-safe components. It processes dynamic signals. the If errors occur, the outputs of the components always go to iogiscli zero (preferred error position). The inputs connected logically in parallel but electrically in series, which are operated by an output signal obtained by breaking a connection

any position at the same time zero signal. More flawed ones Modules of the type required in the circuit were already in the German Offenlegungsschriften 19 33 713, 19 50 330, 19 50 331, 20 14 135 and 20 H MO described.

It goes without saying that static signals can also be fed to the circuit; in this case a conversion of the static signals into dynamic signals and vice versa at the output Conversion of dynamic signals into static signals.

£ ur display of an error in the clock signal Γ was the circuit has a control lamp on signal 6 at the output of the time delay element 7? attached. According to signal 6, this lamp lights up as long as a

■) Normal sequence of the clock signal is present. Only when there is waste of the signal, the control lamp, which works according to the closed-circuit principle, is also switched off. A Failure of the control lamp thus indicates an error in the monitored clock signal Γ or an error in the

ίο used blocks.

For this purpose 2 sheets of drawings

Claims (4)

Patent claims: 1. Electronic circuit made up of fail-safe, alternating current signals; Modules for frequency and phase monitoring of clock pulses and for blocking the transmission of faulty clock pulses, characterized in that a memory (Sp) is set by an acknowledgment signal (Q) and remains set as long as the clock pulses arrive within a time interval ff 2) that from two time delay elements triggered by the previous clock pulse (T ₁ , T ₂ ) is fixed. 2. Electronic circuit according to claim 1, characterized in that a memory (Sp) is used with reset priority and the memory (Sp) remains set as long as the negated clock signal (T) or the time interval (t 2) determining signal (8 ) is present via OR gates (O ₁ , O ₂ ) at the reset input (R) neg \ ert . 3. An electronic circuit according to claim 1 or 2, characterized in that at a first logical AND gate (U,), the clock signal (T), the output of the memory (Sp) and the time interval (t 1) determining signal (8 ) is applied, so when the logical AND condition is fulfilled, the clock pulse (T ) pending at the output of the AND element (U, ) triggers a time delay element (T,) and thus a second AND element (U ₂ ), which causes a The time delayed signal (6) generated by the time delay element (Ti) and triggered by the previous clock pulse, which is reduced by the duration of the clock pulse via a third AND element (U ₃ ) , on the one hand via an OR element (Οχ) to the first AND element (U,) and on the other hand negated is supplied to the second AND element (Ui) , the time delay element (T,) is triggered again. 4. Electronic circuit according to one of claims 1, 2 or 3, characterized in that a control lamp ^ is connected to the output of the time delay element (T ₂ ).