GB1286737A - Multilevel conductive systems - Google Patents

Multilevel conductive systems

Info

Publication number
GB1286737A
GB1286737A GB47462/70A GB4746270A GB1286737A GB 1286737 A GB1286737 A GB 1286737A GB 47462/70 A GB47462/70 A GB 47462/70A GB 4746270 A GB4746270 A GB 4746270A GB 1286737 A GB1286737 A GB 1286737A
Authority
GB
United Kingdom
Prior art keywords
conductors
channels
silicon
oct
insulating layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB47462/70A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH, ITT Industries Inc filed Critical Deutsche ITT Industries GmbH
Publication of GB1286737A publication Critical patent/GB1286737A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
GB47462/70A 1969-10-15 1970-10-06 Multilevel conductive systems Expired GB1286737A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US86655569A 1969-10-15 1969-10-15

Publications (1)

Publication Number Publication Date
GB1286737A true GB1286737A (en) 1972-08-23

Family

ID=25347860

Family Applications (1)

Application Number Title Priority Date Filing Date
GB47462/70A Expired GB1286737A (en) 1969-10-15 1970-10-06 Multilevel conductive systems

Country Status (3)

Country Link
DE (1) DE2049908B2 (enExample)
FR (1) FR2066013A5 (enExample)
GB (1) GB1286737A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0101960A1 (en) * 1982-07-30 1984-03-07 Hitachi, Ltd. Method of manufacturing a semiconductor device having a self-aligned gate electrode
US5063175A (en) * 1986-09-30 1991-11-05 North American Philips Corp., Signetics Division Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
US5084414A (en) * 1985-03-15 1992-01-28 Hewlett-Packard Company Metal interconnection system with a planar surface
EP0262719B1 (en) * 1986-09-30 1993-12-15 Koninklijke Philips Electronics N.V. Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4960870A (enExample) * 1972-10-16 1974-06-13
US3844831A (en) * 1972-10-27 1974-10-29 Ibm Forming a compact multilevel interconnection metallurgy system for semi-conductor devices
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface
US4035276A (en) * 1976-04-29 1977-07-12 Ibm Corporation Making coplanar layers of thin films
DE3228399A1 (de) * 1982-07-29 1984-02-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen einer monolithisch integrierten schaltung
JPS5982746A (ja) * 1982-11-04 1984-05-12 Toshiba Corp 半導体装置の電極配線方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0101960A1 (en) * 1982-07-30 1984-03-07 Hitachi, Ltd. Method of manufacturing a semiconductor device having a self-aligned gate electrode
US5084414A (en) * 1985-03-15 1992-01-28 Hewlett-Packard Company Metal interconnection system with a planar surface
US5063175A (en) * 1986-09-30 1991-11-05 North American Philips Corp., Signetics Division Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
EP0262719B1 (en) * 1986-09-30 1993-12-15 Koninklijke Philips Electronics N.V. Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material

Also Published As

Publication number Publication date
DE2049908B2 (de) 1976-03-25
DE2049908A1 (de) 1971-04-22
FR2066013A5 (enExample) 1971-08-06

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees