GB1258892A - - Google Patents
Info
- Publication number
- GB1258892A GB1258892A GB1258892DA GB1258892A GB 1258892 A GB1258892 A GB 1258892A GB 1258892D A GB1258892D A GB 1258892DA GB 1258892 A GB1258892 A GB 1258892A
- Authority
- GB
- United Kingdom
- Prior art keywords
- control input
- stage
- counter
- counting
- gray code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/14—Conversion to or from non-weighted codes
- H03M7/16—Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/004—Counters counting in a non-natural counting order, e.g. random counters
- H03K23/005—Counters counting in a non-natural counting order, e.g. random counters using minimum change code, e.g. Gray Code
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
Abstract
1,258,892. Selective signalling. IMPERIAL CHEMICAL INDUSTRIES Ltd. 8 Jan., 1969 [10 Jan., 1968], No. 1439/68. Headings G4A and G4H. The Gray code output of a counter comprising JK flip-flops F a -F c is converted to binary by exclusive OR gates connected as shown, the least significant bit a, of which (representing the Gray code parity) determines the direction of counting in conjunction with a control input applied to a further exclusive OR gate. The counter is constrained to assume Gray code states in response to successive input pulses by the intermediate gates (NAND or NOR) which enable a stage to change state only when the next lower stage holds a 1 and all the other preceding stages hold a 0. The direction control is based on the fact that for each input pulse, a change in state in stage F a effects a count up or down depending on whether the existing parity is even or odd, the reverse being the case for all other stages, and an additional inverting gate is therefore included in the control input to F a . By imposing a 1 on the control input, the effective parity is reversed and the direction of counting is also reversed. An additional stage F, Fig. 5 (not shown) can automatically reverse the counting direction on overflow, and a counter of this type may provide the control input to a number of slave counters forming part of a telemetering scanner.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1433968 | 1968-01-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1258892A true GB1258892A (en) | 1971-12-30 |
Family
ID=10039403
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1258892D Expired GB1258892A (en) | 1968-01-10 | 1968-01-10 |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1258892A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0630116A2 (en) * | 1990-03-01 | 1994-12-21 | Hewlett-Packard Company | Integrated high speed synchronous counter with asynchronous read-out |
-
1968
- 1968-01-10 GB GB1258892D patent/GB1258892A/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0630116A2 (en) * | 1990-03-01 | 1994-12-21 | Hewlett-Packard Company | Integrated high speed synchronous counter with asynchronous read-out |
EP0630116A3 (en) * | 1990-03-01 | 1995-05-03 | Hewlett Packard Co | Integrated high speed synchronous counter with asynchronous read-out. |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PE20 | Patent expired after termination of 20 years |