GB1257124A - - Google Patents

Info

Publication number
GB1257124A
GB1257124A GB1257124DA GB1257124A GB 1257124 A GB1257124 A GB 1257124A GB 1257124D A GB1257124D A GB 1257124DA GB 1257124 A GB1257124 A GB 1257124A
Authority
GB
United Kingdom
Prior art keywords
time
incoming
delay
pairs
outgoing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1257124A publication Critical patent/GB1257124A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/06Time-space-time switching
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/062Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0676Mutual

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

1,257,124. Automatic exchange systems. SIEMENS A.G. 1 Oct., 1969 [2 Oct., 1968], No. 48140/69. Heading H4K. In a TDM systemhaving 4-wire highways between exchanges, the time frames on all the incoming pairs to any one exchange are synchronized to each other as also are the frames on all the outgoing pairs, the latter frames being delayed by a period tv relative to the incoming ones. Time slot interchange is effected by delaying a channel in one direction through an exchange by a time tx and by delaying the corresponding channel in the other direction by a time ty such that tx + ty = 2tv. In Fig. 1 mutual synchronization of the incoming pairs Aan1, Aan2 to exchange A is effected by delay devices Vab and Vac, the other incoming highways and the outgoing highways being similarly synchronized by devices not shown. In Fig. 2a it can be seen that a time frame T on incoming pairs Aan1, Aan2 leads the corresponding frame on outgoing pairs Aab2, Aab1 by a time tv. An incoming PCM channel, depicted by a single pulse on Aan1 is delayed by a time tx before it is relayed along an outgoing pair Aab2 in the required direction. In the opposite direction, the corresponding channel is delayed by a time ty between incoming pair Aan2 and outgoing pair Aab1. As already mentioned tx+ty=2tv. The dotted pulses indicate the case when tx=2tv and ty=0. The delay may be effected by devices Vab etc. or by separate store pairs (one for each direction) having a total delay of 2tv. Since there are inevitably some channels which cannot conform to the above rule these are handled by stores having a delay of T+2tv (Fig. 2b, not shown). Overall the number of long-delay stores required is very small. Since the short-delay stores may be utilized more than once in a frame, the total number of stores required is much reduced compared with previous time slot interchange systems.
GB1257124D 1968-10-02 1969-10-01 Expired GB1257124A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE1800726 1968-10-02

Publications (1)

Publication Number Publication Date
GB1257124A true GB1257124A (en) 1971-12-15

Family

ID=5709404

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1257124D Expired GB1257124A (en) 1968-10-02 1969-10-01

Country Status (13)

Country Link
JP (1) JPS5038285B1 (en)
AT (1) AT300906B (en)
BE (1) BE739731A (en)
CH (1) CH518657A (en)
DE (1) DE1800726B1 (en)
DK (1) DK131450B (en)
FR (1) FR2019667A1 (en)
GB (1) GB1257124A (en)
LU (1) LU59536A1 (en)
NL (1) NL6914413A (en)
RO (1) RO64752A (en)
SE (1) SE362181B (en)
SU (1) SU608491A3 (en)

Also Published As

Publication number Publication date
DK131450B (en) 1975-07-14
LU59536A1 (en) 1970-01-09
AT300906B (en) 1972-08-10
RO64752A (en) 1978-11-15
DE1800726B1 (en) 1970-05-27
BE739731A (en) 1970-04-02
SU608491A3 (en) 1978-05-25
CH518657A (en) 1972-01-31
FR2019667A1 (en) 1970-07-03
SE1352469A (en) 1973-11-26
DK131450C (en) 1975-12-01
NL6914413A (en) 1970-04-06
SE362181B (en) 1973-11-26
JPS5038285B1 (en) 1975-12-09

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees