GB1274960A - Improvements in or relating to time-division multiplex telecommunications exchange systems - Google Patents
Improvements in or relating to time-division multiplex telecommunications exchange systemsInfo
- Publication number
- GB1274960A GB1274960A GB4396170A GB4396170A GB1274960A GB 1274960 A GB1274960 A GB 1274960A GB 4396170 A GB4396170 A GB 4396170A GB 4396170 A GB4396170 A GB 4396170A GB 1274960 A GB1274960 A GB 1274960A
- Authority
- GB
- United Kingdom
- Prior art keywords
- gates
- pairs
- pair
- delay
- incoming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
- H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0676—Mutual
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/06—Time-space-time switching
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
1,274,960. Automatic exchange systems. SIEMENS A.G. 15 Sept., 1970 [16 Sept., 1969], No. 43961/70. Addition to 1,257,214. Heading H4K. In a TDM system having 4-wire highways between exchanges, the time frames on all the incoming pairs to any one exchange are synchronized to each other as also are the frames on all the outgoing pairs, the latter frames being delayed by a period tv relative to the incoming ones. Time slot interchange is effected by pairs of delay circuits, one circuit of a pair delaying a channel in one direction by a time tx and the other circuit delaying the corresponding channel in the other direction by a time ty where tx + ty = 2tv. The wire pairs are connected to the delay circuits via gates which are controlled by only one recirculating type memory per highway. The outputs of the memory are applied to the gates on the incoming pair side of the delay circuits immediately they are produced but are applied to the gates on the outgoing pair side of the delay circuits after a delay equal to tv. As shown, the incoming (PCM) pairs ZMLanI to ZMLanN are connectable via associated sets of gates, Ik0 ... Ik3<SP>1</SP> to Nk0 ... Nk3<SP>1</SP>, to pairs of delay circuits Z0/Z6 ... Z3/Z3<SP>1</SP> to the outputs of which the outgoing pairs ZMLabI to ZMLabN are connectable via sets of gates 6kI ... 3kI to 6kN ... 3kN. The delay pair Z0/Z6 provide delays of tx = 0, ty = 2tv respectively while the pair Z3/Z3<SP>1</SP> provide delays of tx=tv, ty=tv respectively, other combinations of tx and ty being provided by the not shown intervening pairs. The incoming pair ZMLanI and the outgoing pair ZMLabI of a same highway have an associated recirculating memory UI whose output in a particular time slot immediately controls via decoder DanI one of gates Ik0 ... Ik3<SP>1</SP> while its decoded output (DabI) from the same time slot controls one of gates 6kI ... 3kI after a delay (=tv) provided by a delay circuit Vtv. In operation a connection between calling highway ZMLanI/ZMLabI and called highway ZMLanN/ ZMLabN is set-up by allocating a delay pair e.g. Z0/Z6 which will provide the desired time slot matching for the two channels to be used on the highways and by inserting the appropriate gating instructions in UI and UN. In the example, these comprise opening gates Ik0 and OkN simultaneously for the calling to call speech direction and opening Nk6 and 6kI with a time separation equal to tv for the called to calling speech direction, this being affected by inserting the instruction in UN such that it emanates therefrom at a time which leads by tv the corresponding instruction from UI. If the pair Z3/Z3<SP>1</SP> i.e. tx=tt=tv, had been used then the instructions would be inserted simultaneously into the memories UI, UN. In the event that delays longer than 2tv are necessary to effect time slot interchange, additional static memories ZV, ZV<SP>1</SP> are provided. Access to these is obtained via gates vkV ... Vkv which are controlled by memory UV and decoders DanV, DabV in a manner similar to that described above. Only one intermediate line between all the gates Ikv ... Nkv pertaining to the incoming pairs and the gates vkV ... ukV<SP>1</SP> (and similarly for the outgoing pairs) is needed in this case.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE1800726 | 1968-10-02 | ||
DE19691946883 DE1946883B2 (en) | 1968-10-02 | 1969-09-16 | CIRCUIT ARRANGEMENT FOR RECORDING AND REPLAYING MESSAGE SIGNALS IN PARTICULAR PCM SIGNALS IN TIME MULTIPLEX SWITCHING POINTS OF A TIME MULTIPLEX IN PARTICULAR PCM TIME MULTIPLEX REMOTE INFORMATION NETWORK |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1274960A true GB1274960A (en) | 1972-05-17 |
Family
ID=25756202
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4396170A Expired GB1274960A (en) | 1968-10-02 | 1970-09-15 | Improvements in or relating to time-division multiplex telecommunications exchange systems |
Country Status (8)
Country | Link |
---|---|
AT (1) | AT313377B (en) |
BE (1) | BE756231R (en) |
CH (1) | CH584486A5 (en) |
DE (1) | DE1946883B2 (en) |
FR (1) | FR2066913B2 (en) |
GB (1) | GB1274960A (en) |
LU (1) | LU61684A1 (en) |
NL (1) | NL7013200A (en) |
-
0
- BE BE756231A patent/BE756231R/en active
-
1969
- 1969-09-16 DE DE19691946883 patent/DE1946883B2/en not_active Withdrawn
-
1970
- 1970-09-07 NL NL7013200A patent/NL7013200A/xx unknown
- 1970-09-14 LU LU61684A patent/LU61684A1/xx unknown
- 1970-09-14 AT AT830470A patent/AT313377B/en not_active IP Right Cessation
- 1970-09-15 GB GB4396170A patent/GB1274960A/en not_active Expired
- 1970-09-15 CH CH1363470A patent/CH584486A5/xx unknown
- 1970-09-15 FR FR7033405A patent/FR2066913B2/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
LU61684A1 (en) | 1970-12-21 |
AT313377B (en) | 1974-02-11 |
DE1946883B2 (en) | 1971-12-30 |
FR2066913A2 (en) | 1971-08-13 |
NL7013200A (en) | 1971-03-18 |
DE1946883A1 (en) | 1971-04-15 |
BE756231R (en) | 1971-03-16 |
FR2066913B2 (en) | 1973-01-12 |
CH584486A5 (en) | 1977-01-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PLNP | Patent lapsed through nonpayment of renewal fees |