GB1242121A - Improvements in or relating to calculating machine - Google Patents

Abstract

1,242,121. Digital calculators. BELL PUNCH CO. Ltd. 26 Feb., 1969 [1 March, 1968], No. 10002/68. Heading G4A. A calculating machine comprises a multistage register and a multi-stage display device for displaying its contents, and means for detecting the presence of a digit of predetermined value at a particular register stage and thereupon operating means for transferring digits between register stages so that the most significant digit of the register contents is displayed at a predetermined stage of the display device .. Timing.-An oscillator drives a first Johnson ring counter which each cycle marks 10 leads in turn, produces a shift pulse for the input and accumulator registers (see below), increments a second Johnson ring counter and produces various derived pulses. Input.-Operation and digit entry keyboards are provided, fed by the 10 leads mentioned above of the first ring, entered digits being represented by equal-valued pulses. Registers and decimal points.-An accumulator register consists of four loop shift registers arranged in parallel to hold a series of binarycoded-decimal digits, a four-stage decade counter being constituted by a corresponding stage from each register and having two carry bi-stables. An input register is like the accumulator register. Each register is recirculated by the shift pulses. A net shift of one place to left or right is achieved by suppressing a shift pulse or inserting an extra shift pulse respectively. A decimal point (position) counter is also provided. Multiplication.-The multiplier digits are taken, low order first, in turn from the accumulator register and put in tens-complement form into a buffer counter, the multiplicand from the input register being added to a partial product in the accumulator register with incrementing of the buffer counter until it goes to zero when the input register shifts one place to the left and the next multiplier digit is taken. If there is high-order overflow of any (partial) product, the accumulator register is shifted one place to the right under control of one of its carry bi-stables (see above). Division.-Starting with the dividend in the accumulator register and the divisor in the input register, the quotient is built up in the accumulator register by repeated subtraction with restoration and.divisor shift, utilizing the buffer counter to receive successive dividend digits (increased by one), most significant first. A dummy position is provided for the quotient at high order, holding zero. The first divisor subtraction should cause the buffer counter to reach zero. If it does not, the accumulator register is shifted one place to the right and the division routine starts again. This facility compensates for the possibility of the divisor being some way down the input register with its consequence of quotient overflow. Addition.-After aligning decimal points by relative shift, a number in the input register can be added into the accumulator register. A high order overflow (to the accumulator register carry bi-stables) causes the accumulator register to shift one place to the right. The decimal point counter is also adjusted. Subtraction is by complementary addition. Output.-The contents of the accumulator or input register, as selected by a bi-stable, are displayed on a bank of number-indicating tubes and a bank of associated decimal-point neon tubes. The decade counter forming a part of the register receives the digits in turn, a train of oscillator pulses being used, in each case, to increment the counter until it reaches zero when the remaining pulses in the train increment the buffer counter, the final count of which, equal to the digit, is passed to a staticizer. The decimal point position is passed to the staticizer similarly, by incrementing the decimal point counter and then the buffer counter. The second Johnson ring selects in turn, the bank of neon tubes, then the individual number-indicating tubes, the concurrent contents of the staticizer; representing the decimal point position and the successive digits respectively, causing energization of one of the neon tubes and an appropriate cathode in each number-indicating tube. By suppressing shift pulses to the register and pulses to the decimal point counter, left shifts are achieved, repeated until the decimal point count is zero at the left hand end and the accumulator register has no carry out of the digit order corresponding to the leftmost number-indicating tube, so the number is displayed justified to the left.