GB1261710A - Improvements in or relating to calculating machines - Google Patents

Abstract

1,261,710. Digital calculator. BELL PUNCH CO. Ltd. 7 July, 1969 [18 July, 1968], No. 34314/68. Heading G4A. A digital electronic calculator for the four arithmetic operations comprises two multi-stage shift registers 24, 38 and circuitry for controlling the relative shift of the registers. Before an arithmetic operation commences, clock pulses from a source comprising an oscillator 1, a timer 12 and a Johnson decade counter 2 produce a regular shift pulse dp9 every ten clock pulses which drives the contents of the registers round in synchronism. Each register comprises four register stages, e.g. 25a, 25b, 25c, 25d, each stage comprising 12 digit stages and a thirteenth stage in buffer 26. On depressing an arithmetic function key, every thirteenth shift pulse an extra shift pulse goes to register 24, hence register 24 shifts to the right with respect to register 38, and this happens eleven times. Then every thirteenth shift pulse to register 24 is suppressed so that register 24 shifts left into synchronism with register 38 again after thirteen suppressions. Alternatively pulses are added to or subtracted from register 38. Division occurs during the right shift, multiplication during the left shift, and addition and subtraction when the registers have been repositioned so that their corresponding stages are in alignment. The operands are entered on a keyboard and a visual display shows the magnitude and decimal point of the result. The numerals are in binary coded decimal. Multiplication.-The multiplier is in register 38, the multiplicand is register 24 and the product stored in register 38 before display. The. tens complement of the least significant digit in the register 38 is entered into a buffer 20 and the. left shift is ceased by a bi-stable 66. Then the number in register 24 is added into register 38 by the ten clock pulses and the number in buffer 20 increased by one until it reaches ten. The register 24 is shifted one. place left by bi-stable 66 and the process repeated. The decimal point of the product is calculated in the counter 56 by adding the decimal places of the operands. If the product is too large for register 38 then the latter is shifted one place right and the least significant digit dropped. Division.-The dividend is in register 38, the divider in register 24 and the quotient stored in register 38. Firstly the register 38 is shifted right to move the dividend into position then division is carried out by repeated subtraction using tens complementing. When the remainder goes negative the divisor is added back again once, register 24 is shifted one place rightwards and the process repeated. When ten digits of quotient have been calculated the input register 24 shifts into alignment with register 38, the decimal point is calculated and the quotient displayed. Addition, subtraction.-The registers are first aligned by comparing the decimal point counts of the numbers and moving register 24 or 38 accordingly and the numbers added by the 10 clock pulses. Subtraction is carried out in a similar manner using the nines complement method.