US3641561A

US3641561A - Display system for use in desk top computers

Info

Publication number: US3641561A
Application number: US798407A
Authority: US
Inventors: Kinichiro Osugi; Yoshiaki Suzuki; Tokio Mori; Toshiharu Inamoto
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 1968-02-28
Filing date: 1969-02-11
Publication date: 1972-02-08
Anticipated expiration: 1989-02-08
Also published as: CH524202A; SE342105B; BE729045A; NO126405B; NL6903163A; GB1244515A; FR2002782A1; DE1908869A1; DK122045B

Abstract

A display system for use in a serial-type desk top computer having a recirculating shift register and a plurality of coldcathode gas readout tubes adapted to indicate information stored in the register sequentially. The system includes in combination a clock pulse generator operating the register, incremental and decremental counters connected to receive the output of the pulse generator, a coincidence circuit receiving the outputs of the register and both counters at its input side and providing a signal to light a corresponding one of the tubes so that the information may be displayed on the tubes from the most significant character to the least significant character successively for a display period of time sufficiently long to be visually recognized for each character being displayed thereon.

Description

United States Patent 7 Osugi et al.

[ Feb. 8, 1972 [S4] DISPLAY SYSTEM FOR USE IN DESK TOP COMPUTERS [72] Inventors: Klnichiro Osugi, Yokohama-shi; Yoshiaki Suzuki, Tokyo; Tokio Mari; Toshiharu Inamoto, both of Yokohama, all of Japan [73] Assignee: Matsushlta Electric Industrial Co., Ltd.,

Osaka, Japan [22] Filed: Feb. 11, 1969 [21 Appl. No.5 798,407

Primary Examiner-John W. Caldwell Assistant Examiner-Marshall M. Curtis Attorney-Stevens, Davis, Miller & Mosher s71 ABSTRACT A display system for use in a serial-type desk top computer having a recirculating shift register and a plurality of coldcathode gas readout tubes adapted to indicate information stored in the register sequentially. The system includes in combination a clock pulse generator operating the register, incremental and decremental counters connected to receive the output of the pulse generator, a coincidence circuit receiving the outputs of the register and both counters at its input side and providing a signal to light a corresponding one of the tubesso that the information may be displayed on the tubes from the most significant character to the least significant character successively for a display period of time sufficiently [56] R'eferm cued long to be visually recognized for each character being dis- UNITED STATES PATENTS P y h 3,324,458 6/1967 MacArthur ......?40/324 A 4 Claims, 7 Di Figures REG/5 TER 6/. 06K f5? PULSE GENERATOR mun/rm. CUINCIDENCE CIRCUIT CIRCUIT D/5PLAY '55\ 001mm? BUFFER DISPLAY a DISPLAY SYSTEM FOR USE IN DESK TOP COMPUTERS The present invention relates to a display system for use in a serial-type desk top computer, and more particularly to an improvement in display systems for displaying information stored in a recirculating shift register.

In a prior art system, when thenumber of character positions in a register is five, i.e., L, 2, 3, 4 and M, as shown in FIG. I, the contents of the register are displayed successively in the order of L, 2, 3, 4 and M, by use of a dynamic (anode switching) display system. Further, there has been disclosed a so-called static-display system in which the contents of a register can be displayed simultaneously, using a buffer having the same number of character positions as in the register. But in these cases, the former has the defect that the display is completed merely for a very short period of time because the display time of each character position is one-fifth of the whole time. The latter needs a highly complex buffer to memorize the contents of the register temporarily. In both cases, it is difficult to display the contents of the register from the most significant character position to the least significant character position successively because it picks up the contents of the register from the least significant character position to the most significant character position in turn.

Therefore, one object of the present invention is to provide an improved display system for use in a desk top computer, which system is capable of controlling the display of information registered in a shift register with ease.

Another object of the present invention is to provide an improved display system which is capable of displaying the contents of the register from the most significant character position to the least significant character position successively.

Now the present invention will be described in detail in conjunction with the accompanying drawings, in which:

FIG. I is a diagram showing a conventional recirculating register;

FIG. 2 is a schematic diagram illustrating a display system according to an embodiment of the present invention; and

FIGS. 3a to 3e are diagrams showing outputs of the blocks shown in FIGS. 2, respectively. I

For the purpose of easy understanding of the invention, description of one embodiment of the present invention will be made with reference to FIGS. 2 and 3 hereunder.

Numeral 51 designates a recirculating shift register having five character positions, i.e.,L, 2, 3, 4'and M, which is of the same type as shown in FIGS. 1. The numeral 52 designates a clock pulse generator providing clock pulses for timing, these pulses being supplied sequentially to the register 51 to shift the contents of the register in turn in the order of L, 2, 3, 4 and M, as shown in FIG. 3b (FIG. 3a illustrates the clock pulses). Numeral 53 denotes an incremental counter circuit which counts the clock pulses in the order L, 2, 3, 4, M, L at a count cycle, the upper limit of each of which is equal to the number of character positions of the register 51 in synchronism with the register 51 as shown in FIG. 3c. Numeral 54 designates a decremental counter which counts decrementally from the uppermost count value of the counter 53 to subtract one pulse count for every n--l pulse count (for example, every count of 4 clock pulses, as shown in FIG. 3d). Numeral 55 denotes a coincidence circuit formed of an AND gate having input terminals connected to the outputs of the register 51, incremental counter 53 and decremental counter 54, the coincidence circuit comparing an output of the incremental counter 53 with that of the decremental counter 54 and giving an output corresponding to a specified one character position of the register when the count values of the both counters coincide with each other. Numeral 56 is a buffer activated by operation of the

coincidence circuit

55 and 57 is an indicator means formed of cold-cathode gas readout tubes, such as those sold by the Burroughs Corporation under the trademark Nixie, which tubes are provided corresponding to individual character positions of the register 51. All of the abovedescribeddevices are conventional and generally available.

Next, the operation of the display system will be described. Upon reception of clock pulses from the clock pulse generator 52, as shown in FIG. 3a, the output character positions of the register 51 are shifted and the counter 53 counts the incoming clock pulses, as shown in FIGS. 31) and 30, respectively. Then, a count value of the decremental counter 54 is M when the reading of the counter 54 is not M; that is, when it counts 2, 3 or 4, whereas the indicator means 57 displays L because the decremental counter 54 subtracts one pulse count from the five count value at every reception of 4 pulses.

When the counter 53 counts M, coincidence of the count value at the output of the counter '54 is completed in the coincidence circuit 55. As a result, the circuit 55 provides an output signal gating or the output of the corresponding character position of the register to the buffer 56, and the output of the buffer 56 changes form L to M, as shown in FIG. 3e. Accordingly, the indicator means 57 indicates M position. Even though the count character in the counter 53 is advanced from M to L, 2, 3 and 4 in turn by the reception of the successive clock pulses, the display of the indicator means 57 is not changed due to memory of the buffer 56. When the coincidence is completed again, the display of the indicator means 57 is changed from M to L. The character position to be displayed on the indicator means 57 is in turn changed in the order of 3, 2, L and M, at every count of five clock pulses.

As mentioned above, the present invention provides a serial-display system comprising in combination a recirculating shift register storing information processed by an arithmetic operation circuit to be indicated on an indicator means; an incremental counter which counts clock pulses which shift character positions of said register successively in synchronism with the shifting of said register; a decremental counter which counts in the reverse direction with respect to the uppermost count value of said incremental counter at every count of n-l clock pulses in case the number of character positions in said register is n; and a coincidence circuit which detects the coincidence between outputs of said both counters and provides an output for controlling the indicator means.

Consequently, information existing in one character position of the register is indicated in the indicator means every one cycle of the register, even though the speed of the clock pulse is too fast. Thus, the display of the registered information can certainly be achieved. Simultaneously, sequential display from the most significant character position to the least significant character position is possible. Although it has been shown that information stored in one character position of the register is displayed every one cycle in said embodiment, the information can be displayed every n cycles if the coincidence is completed every n cycles.

What is claimed is:

1. In a display system for use in a serial-type desk top computer including therein a recirculating shift register for temporarily storing in a plurality of digit positions information processed by an arithmetic operation circuit of the computer, and indicator tubes which are substantially equal in number to that of said digit positions and associated with the outputs of said digit positions individually so as to indicate said stored information on the corresponding tubes sequentially, the improvement comprising a clock pulse generator generating clock pulses and coupled with the register to feed thereto the generated pulses as carry ones for said digit positions; an incremental counter counting the clock pulses at a predetermined count cycle having an uppermost count value which is equal to the number of said digit positions; a decremental counter connected in parallel with said incremental counter to the output of said clock generator for counting decrementally from the count number of said uppermost count value line for every one count cycle which is equal to said predetermined count cycle by an integer number, and in synchronism with the shifting of said register conducted in response to the reception of the clock pulses; a coincidence circuit having its input terminals connected to the output of said shift register and the outputs of said both counters for transmitting a character signal located on the character position of the re gister when the output values of both the counters coincide with each other, a buffer circuit provided between the output of said coincidence circuit and said indicator tubes to receive, hold, and feed said transmitted signal to said indicator tubes to light a corresponding one of said tubes until receiving a subsequent character signal, the information stored in the register being displayed in turn from the most significant character to the least significant character successively with a required delay associated with the shifting cycle of the register.

2. The improvement according to claim 1, in which said decremental counter is adapted to start a new count cycle

Claims

1. In a display system for use in a serial-type desk top computer including therein a recirculating shift register for temporarily storing in a plurality of digit positions information processed by an arithmetic operation circuit of the computer, and indicator tubes which are substantially equal in number to that of said digit positions and associated with the outputs of said digit positions individually so as to indicate said stored information on the corresponding tubes sequentially, the improvement comprising a clock pulse generator generating clock pulses and coupled with the register to feed thereto the generated pulses as carry ones for said digit positions; an incremental counter counting the clock pulses at a predetermined count cycle having an uppermost count value which is equal to the number of said digit positions; a decremental counter connected in parallel with said incremental counter to the output of said clock generator for counting decrementally from the count number of said uppermost count value one for every one count cycle which is equal to said predetermined count cycle by an integer number, and in synchronism with the shifting of said register conducted in response to the reception of the clock pulses; a coincidence circuit having its input terminals connected to the output of said shift register and the outputs of said both counters for transmitting a character signal located on the character position of the register when the output values of both the counters coincide with each other, a buffer circuit provided between the output of said coincidence circuit and said indicator tubes to receive, hold, and feed said transmitted signal to said indicator tubes to light a corresponding one of said tubes until receiving a subsequent character signal, the information stored in the register being displayed in turn from the most significant character to the least significant character successively with a required delay associated with the shifting cycle of the register.

2. The improvement according to claim 1, in which said decremental counter is adapted to start a new count cycle when said incremental counter has effected predetermined count cycles so that the display rate of the information may be selected.

3. The improvement according to claim 1, in which the output of said decremental counter is supplied to said buffer circuit and said indicator tubes to reset them together with self-resetting of the counter at every termination of its count cycle.

4. The improvement according to claim 1, in which each of said indicator tubes is of a cold-cathode gas readout tube.