GB1231543A - - Google Patents

Info

Publication number
GB1231543A
GB1231543A GB1231543DA GB1231543A GB 1231543 A GB1231543 A GB 1231543A GB 1231543D A GB1231543D A GB 1231543DA GB 1231543 A GB1231543 A GB 1231543A
Authority
GB
United Kingdom
Prior art keywords
zone
type
base
diffused
april
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1231543A publication Critical patent/GB1231543A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions

Landscapes

  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
GB1231543D 1968-04-27 1969-04-24 Expired GB1231543A (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE1769271A DE1769271C3 (de) 1968-04-27 1968-04-27 Verfahren zum Herstellen einer Festkörperschaltung

Publications (1)

Publication Number Publication Date
GB1231543A true GB1231543A (https=) 1971-05-12

Family

ID=5700073

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1231543D Expired GB1231543A (https=) 1968-04-27 1969-04-24

Country Status (4)

Country Link
CH (1) CH490737A (https=)
DE (1) DE1769271C3 (https=)
FR (1) FR2007542A1 (https=)
GB (1) GB1231543A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4132573A (en) * 1977-02-08 1979-01-02 Murata Manufacturing Co., Ltd. Method of manufacturing a monolithic integrated circuit utilizing epitaxial deposition and simultaneous outdiffusion

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2608267A1 (de) * 1976-02-28 1977-09-08 Itt Ind Gmbh Deutsche Verfahren zum herstellen einer monolithisch integrierten schaltung
DE2710878A1 (de) * 1977-03-12 1978-09-14 Itt Ind Gmbh Deutsche Verfahren zum herstellen einer an der oberflaeche eines halbleiterkoerpers aus silicium liegenden zone einer monolithisch integrierten i hoch 2 l-schaltung

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4132573A (en) * 1977-02-08 1979-01-02 Murata Manufacturing Co., Ltd. Method of manufacturing a monolithic integrated circuit utilizing epitaxial deposition and simultaneous outdiffusion

Also Published As

Publication number Publication date
CH490737A (de) 1970-05-15
DE1769271A1 (de) 1970-12-17
DE1769271B2 (de) 1973-11-22
DE1769271C3 (de) 1975-04-30
FR2007542A1 (https=) 1970-01-09

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
435 Patent endorsed 'licences of right' on the date specified (sect. 35/1949)
PCNP Patent ceased through non-payment of renewal fee