GB1231543A - - Google Patents
Info
- Publication number
- GB1231543A GB1231543A GB1231543DA GB1231543A GB 1231543 A GB1231543 A GB 1231543A GB 1231543D A GB1231543D A GB 1231543DA GB 1231543 A GB1231543 A GB 1231543A
- Authority
- GB
- United Kingdom
- Prior art keywords
- zone
- type
- base
- diffused
- april
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19681769271 DE1769271C3 (de) | 1968-04-27 | 1968-04-27 | Verfahren zum Herstellen einer Festkörperschaltung |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1231543A true GB1231543A (es) | 1971-05-12 |
Family
ID=5700073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB1231543D Expired GB1231543A (es) | 1968-04-27 | 1969-04-24 |
Country Status (4)
| Country | Link |
|---|---|
| CH (1) | CH490737A (es) |
| DE (1) | DE1769271C3 (es) |
| FR (1) | FR2007542A1 (es) |
| GB (1) | GB1231543A (es) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4132573A (en) * | 1977-02-08 | 1979-01-02 | Murata Manufacturing Co., Ltd. | Method of manufacturing a monolithic integrated circuit utilizing epitaxial deposition and simultaneous outdiffusion |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2608267A1 (de) * | 1976-02-28 | 1977-09-08 | Itt Ind Gmbh Deutsche | Verfahren zum herstellen einer monolithisch integrierten schaltung |
| DE2710878A1 (de) * | 1977-03-12 | 1978-09-14 | Itt Ind Gmbh Deutsche | Verfahren zum herstellen einer an der oberflaeche eines halbleiterkoerpers aus silicium liegenden zone einer monolithisch integrierten i hoch 2 l-schaltung |
-
1968
- 1968-04-27 DE DE19681769271 patent/DE1769271C3/de not_active Expired
-
1969
- 1969-04-24 GB GB1231543D patent/GB1231543A/en not_active Expired
- 1969-04-24 CH CH622669A patent/CH490737A/de not_active IP Right Cessation
- 1969-04-25 FR FR6913186A patent/FR2007542A1/fr not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4132573A (en) * | 1977-02-08 | 1979-01-02 | Murata Manufacturing Co., Ltd. | Method of manufacturing a monolithic integrated circuit utilizing epitaxial deposition and simultaneous outdiffusion |
Also Published As
| Publication number | Publication date |
|---|---|
| DE1769271C3 (de) | 1975-04-30 |
| FR2007542A1 (es) | 1970-01-09 |
| DE1769271A1 (de) | 1970-12-17 |
| DE1769271B2 (de) | 1973-11-22 |
| CH490737A (de) | 1970-05-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| 435 | Patent endorsed 'licences of right' on the date specified (sect. 35/1949) | ||
| PCNP | Patent ceased through non-payment of renewal fee |