GB1221353A - Improvements in or relating to circuit arrangements for multiplicative mixing of electrical signals - Google Patents

Abstract

1,221,353. FET mixing circuits. FERNSEH G.m.b.H. 18 March, 1968 [16 March, 1967], No. 13035/68. Headings H3T and H4R. [Also in Division G4] A mixer circuit has one signal applied to the source-drain path of a field effect transistor, the source and drain electrodes of which are maintained at an equal potential the signal passed by said path being dependant on the signal voltage applied to the gate of the FET. In Fig. 1 a first signal is applied to terminal 1 and hence via transistor 3 to the source of FET 10. A second signal is applied from terminal 11 to the gate electrode 13 which is tied to earth via resistor 14. The FET acts as a variable resistance, its value depending on the gate potential applied such that the output signal from the collector of transistor 6 or 3, appearing across the load 15 or 15<SP>1</SP> represents the product of the two applied signals. Points 8 and 9 are held at equal potentials in the absence of an input signal. The potential applied to the gate can be obtained from several alternative sources. In Fig. 2 a variable direct voltage applied to gate 13 is used for local or remote gain control. For remote control a lead is attached to the gate 13 and hence to the external control circuits. The input resistance of the FET is very high such that the power consumption of the control circuit is very small. In Figs. 3 and 4 (not shown) the gate potential is tapped from a load in the emitter or collector circuit respectively of transistor 3. The circuit of Fig. 4 can produce a non-linear transmission characteristic and it includes a negative temperature coefficient resistor to off-set the temperature dependance of the FET. Fig. 5 may be used for the compensation of spurious signals appearing in picture signal sources and includes a further transistor 43 to maintain a fixed base potential at transistor 42 by means of clamping pulses. The input picture signal is applied at 40 and the compensating signal of sawtooth or parabolic waveform applied at 50. The first signal, applied to the base of transistor 42, is taken from its emitter to the base of transistor 54. A fraction of the first signal, determined by the setting of potentiometer 55, is applied to the gate electrode of the FET 48 in order to linearize the transmission characteristic for the first signal. The first signal is also applied to the source drain path of FET 48 via transistor 46, and the second signal applied to the gate via transistor 52. The current in the FET is therefore a product of the values of the first and second signals and is represented by the output at 57 in the collector circuit of transistor 46. Diode 58 stabilizes transistor 52 against temperature variations.