GB1186974A - Improvements in or relating to the Mounting of Integrated Circuit Members. - Google Patents

Improvements in or relating to the Mounting of Integrated Circuit Members.

Info

Publication number
GB1186974A
GB1186974A GB25025/68D GB2502568D GB1186974A GB 1186974 A GB1186974 A GB 1186974A GB 25025/68 D GB25025/68 D GB 25025/68D GB 2502568 D GB2502568 D GB 2502568D GB 1186974 A GB1186974 A GB 1186974A
Authority
GB
United Kingdom
Prior art keywords
bonding pads
printed circuit
conductors
glass
overlying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB25025/68D
Other languages
English (en)
Inventor
Warren Palmer Waters
Richard Joseph Belardi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of GB1186974A publication Critical patent/GB1186974A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/43—Electric condenser making
    • Y10T29/435—Solid dielectric type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49082—Resistor making
    • Y10T29/49099—Coating resistive material on a base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/4998—Combined manufacture including applying or shaping of fluent material
    • Y10T29/49993—Filling of opening

Landscapes

  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)
GB25025/68D 1967-05-25 1968-05-24 Improvements in or relating to the Mounting of Integrated Circuit Members. Expired GB1186974A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US64132567A 1967-05-25 1967-05-25

Publications (1)

Publication Number Publication Date
GB1186974A true GB1186974A (en) 1970-04-08

Family

ID=24571890

Family Applications (1)

Application Number Title Priority Date Filing Date
GB25025/68D Expired GB1186974A (en) 1967-05-25 1968-05-24 Improvements in or relating to the Mounting of Integrated Circuit Members.

Country Status (4)

Country Link
US (1) US3518751A (https=)
DE (1) DE1766297A1 (https=)
GB (1) GB1186974A (https=)
SE (1) SE344870B (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0110285A3 (en) * 1982-11-27 1985-11-21 Prutec Limited Interconnection of integrated circuits
EP0662713A3 (en) * 1993-12-14 1995-08-30 Ibm Minimal collecting areas for ceramic vias in ceramic substrates.

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3680206A (en) * 1969-06-23 1972-08-01 Ferranti Ltd Assemblies of semiconductor devices having mounting pillars as circuit connections
US3795975A (en) * 1971-12-17 1974-03-12 Hughes Aircraft Co Multi-level large scale complex integrated circuit having functional interconnected circuit routed to master patterns
US4631569A (en) * 1971-12-22 1986-12-23 Hughes Aircraft Company Means and method of reducing the number of masks utilized in fabricating complex multi-level integrated circuits
US4309811A (en) * 1971-12-23 1982-01-12 Hughes Aircraft Company Means and method of reducing the number of masks utilized in fabricating complex multilevel integrated circuits
US3868723A (en) * 1973-06-29 1975-02-25 Ibm Integrated circuit structure accommodating via holes
US4234888A (en) * 1973-07-26 1980-11-18 Hughes Aircraft Company Multi-level large scale complex integrated circuit having functional interconnected circuit routed to master patterns
DE2352138A1 (de) * 1973-10-17 1975-04-30 Siemens Ag Verfahren zum herstellen einer halbleiteranordnung
DE3024213C2 (de) 1980-06-27 1982-09-02 Vdo Adolf Schindling Ag, 6000 Frankfurt Verfahren zur Herstellung von auf einen Träger aufgebrachten Leiterbahnen
FR2525389A1 (fr) * 1982-04-14 1983-10-21 Commissariat Energie Atomique Procede de positionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre
DE3481958D1 (de) * 1983-05-24 1990-05-17 Toshiba Kawasaki Kk Integrierte halbleiterschaltungsanordnung.
KR960009090B1 (ko) * 1984-03-22 1996-07-10 에스지에스 톰슨 마이크로일렉트로닉스, 인코 오포레이티드 표준 배열의 접촉 패드를 가진 집적회로
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
DE4200765A1 (de) * 1992-01-14 1993-07-15 Kodak Ag Vorrichtung zum bewegen eines diapositivs in eine bildbuehne und zur aufnahme eines objektivtraegers
US6077766A (en) * 1999-06-25 2000-06-20 International Business Machines Corporation Variable thickness pads on a substrate surface
CN108493402B (zh) * 2018-04-12 2021-04-02 太原科技大学 利用离子束溅射技术制备锂硫电池正极片的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2890395A (en) * 1957-10-31 1959-06-09 Jay W Lathrop Semiconductor construction
LU38614A1 (https=) * 1959-05-06
US3374533A (en) * 1965-05-26 1968-03-26 Sprague Electric Co Semiconductor mounting and assembly method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0110285A3 (en) * 1982-11-27 1985-11-21 Prutec Limited Interconnection of integrated circuits
EP0662713A3 (en) * 1993-12-14 1995-08-30 Ibm Minimal collecting areas for ceramic vias in ceramic substrates.
US5916451A (en) * 1993-12-14 1999-06-29 International Business Machines Corporation Minimal capture pads applied to ceramic vias in ceramic substrates

Also Published As

Publication number Publication date
SE344870B (https=) 1972-05-02
DE1766297A1 (de) 1971-11-18
US3518751A (en) 1970-07-07

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees