FR3130068B1 - Process for manufacturing a via - Google Patents

Process for manufacturing a via Download PDF

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Publication number
FR3130068B1
FR3130068B1 FR2200140A FR2200140A FR3130068B1 FR 3130068 B1 FR3130068 B1 FR 3130068B1 FR 2200140 A FR2200140 A FR 2200140A FR 2200140 A FR2200140 A FR 2200140A FR 3130068 B1 FR3130068 B1 FR 3130068B1
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FR
France
Prior art keywords
layer
etching
stack
cavity
formation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2200140A
Other languages
French (fr)
Other versions
FR3130068A1 (en
Inventor
Marios Barlas
Pascal Gouraud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Original Assignee
STMicroelectronics Crolles 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics Crolles 2 SAS
Priority to EP22210558.7A priority Critical patent/EP4195246A1/en
Priority to US18/075,087 priority patent/US20230178479A1/en
Priority to CN202211556733.4A priority patent/CN116247001A/en
Publication of FR3130068A1 publication Critical patent/FR3130068A1/en
Application granted granted Critical
Publication of FR3130068B1 publication Critical patent/FR3130068B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Procédé de fabrication d'un via La présente description concerne un procédé de fabrication d'un vias conducteur isolé (36) traversant un premier empilement (10') de couches (14, 18) de manière à atteindre une première couche (12), le premier empilement comprenant au moins une deuxième couche conductrice ou semiconductrice (14), le procédé comprenant : a) la formation d'une première cavité dans le premier empilement ; b) la formation d'un deuxième empilement (22) comprenant une troisième couche d'arrêt de gravure (26), et d'une quatrième couche isolante (28) sur les parois et le fond de la première cavité ; c) la gravure d'une deuxième cavité (34) traversant les premier et deuxième empilements ; d) la formation d'une cinquième couche (36) isolante recouvrant le fond de la deuxième cavité ; et e) la gravure anisotrope de la cinquième couche, la gravure étant une gravure sélective du matériau de la cinquième couche par rapport à la troisième couche. Figure pour l'abrégé : Fig. 6Method for manufacturing a via The present description relates to a method for manufacturing an insulated conductive via (36) passing through a first stack (10') of layers (14, 18) so as to reach a first layer (12), the first stack comprising at least a second conductive or semiconductor layer (14), the method comprising: a) the formation of a first cavity in the first stack; b) the formation of a second stack (22) comprising a third etching stop layer (26), and a fourth insulating layer (28) on the walls and the bottom of the first cavity; c) etching a second cavity (34) passing through the first and second stacks; d) the formation of a fifth insulating layer (36) covering the bottom of the second cavity; and e) anisotropic etching of the fifth layer, the etching being selective etching of the material of the fifth layer with respect to the third layer. Figure for abstract: Fig. 6

FR2200140A 2021-12-07 2022-01-10 Process for manufacturing a via Active FR3130068B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP22210558.7A EP4195246A1 (en) 2021-12-07 2022-11-30 Method for manufacturing via
US18/075,087 US20230178479A1 (en) 2021-12-07 2022-12-05 Via manufacturing method
CN202211556733.4A CN116247001A (en) 2021-12-07 2022-12-06 Method for manufacturing through hole

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GR20210100851 2021-12-07
GR20210100851 2021-12-07

Publications (2)

Publication Number Publication Date
FR3130068A1 FR3130068A1 (en) 2023-06-09
FR3130068B1 true FR3130068B1 (en) 2023-11-24

Family

ID=86613227

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2200140A Active FR3130068B1 (en) 2021-12-07 2022-01-10 Process for manufacturing a via

Country Status (1)

Country Link
FR (1) FR3130068B1 (en)

Also Published As

Publication number Publication date
FR3130068A1 (en) 2023-06-09

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