JPS63131537A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To etch to a desired position with good controllability by retaining a first buried film selectively only on a region having a wide groove width to easily flatten the surface with good distribution. CONSTITUTION:The film thickness of a first insulator 3 is formed substantially equally to a groove depth, the insulator 3 is retained selectively only on an element separating region having a wide groove width. Thus, when a second insulating film 5 is deposited, the element separating region having the wide groove width and the film 5 on the element forming region are substantially equal in height. When fluid substance 6 and the film 6 are etched under the conditions of the same etching speed, the etching area of the film 5 is abruptly reduced. Accordingly, the optical intensity of the specific wavelength is abruptly varied. Thus, the end point of etching can be easily detected to be etched uniformly with good control.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.

The present invention relates to a method of manufacturing a semiconductor device suitable for uniformly filling and planarizing an element isolation region with high accuracy in a method of forming an element isolation region by forming a groove in a semiconductor substrate and burying an insulator.

[Conventional technology]

Conventionally, the method of flatly embedding an insulator in a trench provided in an element isolation region is as described in Japanese Patent Laid-Open No. 58-210634, after depositing a first insulator in the trench and over the entire element region. , A second insulating film is selectively deposited or coated on the device isolation region with a wide groove width. 0th step, a fluid material is applied to the entire surface and flattened. 6th step, the fluid material and the first insulating film are deposited or coated. The entire surface is etched by reactive ion etching under the conditions that the second insulator and the second insulator have the same etching rate, and the insulator is buried and planarized.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, it is necessary to make the thickness of the second insulator the same as the depth of the groove for planarization. However, when a fluid material such as a resist is used as the second insulating film, it becomes difficult to maintain uniformity of the film thickness and control the film thickness, such as the film being thick near the element formation region. Furthermore, CVD S is used as the second insulating film.
Using iOz.

Since it is of the same quality as the first insulating film, patterning becomes difficult. Furthermore, when SillN4 is used, three types of film quality, ie, the fluid material, SisMail, and the first insulating film, must be etched at the same etching rate, resulting in problems such as unstable etching.

Furthermore, in the conventional technology, after planarization, when etching the first insulating film, the second insulating film, and the fluid material at the same etching rate, the variations in the etching conditions remain unchanged until the end of etching. There were problems in that it was difficult to obtain a flat structure over the entire surface, and it was difficult to stop etching at a desired position with good control.

The purpose of the present invention is to easily obtain an element isolation structure in which an insulating material is embedded flatly with good reproducibility by easily flattening the surface with good distribution and etching to a desired position with good control. An object of the present invention is to provide a method for manufacturing a semiconductor device that makes it possible to manufacture a semiconductor device.

[Steps to solve problems]

To achieve the above objective, first, a semiconductor substrate resistant etching mask is formed in the element formation region of the semiconductor substrate, and the semiconductor substrate in the element isolation region is selectively etched to form a groove. Depositing a first insulating film. At this time, the film thickness of the first insulating film is made to be almost the same as the groove depth. 6. Next, if necessary, a film is deposited to detect the end point when etching the entire surface flat. 0. It is selectively processed so that the first insulating film and the end point detection film remain in a wide region, for example, in a region where the trench width is wider than the trench depth.

Next, a second insulating film is deposited and the trench is filled. Next, a fluid material is applied or deposited on the entire surface. The surface is flattened. Next, the second insulating film is The entire surface is etched under conditions such that the etching speed of the fluid material and the etching rate of the fluid material are the same. At this time, the etching is stopped when the etching of the second insulating film on the first insulating film and the second insulating film on the element formation region is completed.

Then, since the thickness of the first insulating film is almost the same as the depth of the trench, an element isolation structure with a flat surface can be obtained.
The end point detection film on the first insulating film on the wide element isolation region and the film used as an etching mask on the element formation region are removed. If necessary, the insulating film is etched thinly by wet etching to further smooth the surface.

[Effect]

The film thickness of the first insulator is made approximately equal to the groove depth.

By selectively leaving the first insulating material only in the device isolation region with the wide groove width, when the second insulating film is deposited, the second insulating film on the device isolation region with the wide trench width and the device formation region is separated. The surface heights are approximately equal. This makes it possible to flatten the surface uniformly and with good distribution.

In addition, if etching is performed under conditions such that the fluid material and the second insulating film have the same etching rate until the end point detection film and the film used as a substrate-resistant etching mask on the element formation region are exposed, the second insulating film is etched at the same etching rate. Since the etched area of the film is rapidly reduced, the light intensity of a particular wavelength also changes rapidly. Due to this.

It becomes easy to detect the end point of etching the second insulating film, and etching can be performed uniformly and with good control. In addition, etching conditions can be selected such that the etching speed of the end point detection film and the film used as a substrate-resistant etching mask on the element formation region is slower than the etching speed of the second insulator and fluid material. Variations in the amount of etching due to variations in conditions can be suppressed.

〔Example〕

An embodiment for implementing the method of the present invention will be described below with reference to FIG. First, as shown in FIG. 1(a), a semiconductor substrate 1, for example, has a surface orientation (100).

A P-type silicon substrate 1 having a specific resistance of 100 is prepared.

Next, a film 1 that will serve as a mask for silicon etching is placed on the substrate.
For example, 1500 CVD5i8N42 are deposited.

Next, the CVD 5iaN No. 2 is removed by etching, leaving a portion that will become the element forming region. Thereafter, the silicon substrate 1 is etched by, for example, 1 μm.

Next, as shown in FIG. 1(b), an insulating film, for example, C
V D S i Oz3 is deposited to a thickness of 1 μm. Here it is.

The thickness of this insulating film becomes the thickness of the insulating film on the field. Therefore, by changing this film thickness, the required insulation film thickness can be obtained. Next, 1500 layers of a film different from the insulating film 3, such as polysilicon 4, are deposited.

Next, as shown in FIG. 1(c), selective etching is performed so that the CVD SiOx 3 and polysilicon 4 remain in a region where the groove width is wider than the groove depth. Here, since CVD5iO23 remains on the side surfaces of the trench in the element formation region,
Etching can be performed without side etching or damage caused by etching. Next, as shown in FIG. 1(d), an insulating film, for example, CVD Si
Ox 5 is deposited so that the surface of the substrate is almost flat. Thereafter, a fluid substance such as resist 6 is applied so as to make the CVD5iOzS surface flat. Next, Figure 1 (
As shown in e), resist 6 and CVD S i Ox
CVD51g under the condition that 5 is etched at the same speed.
Etching is performed until Na2 and polysilicon 4 are exposed. At this time, commonly used plasma etching, reactive ion etching, etc. are used for etching.

Further, when the CVD 51gNi2 and the polysilicon 4 are exposed, the light intensity of a specific wavelength changes, so that the etching end point can be easily and accurately detected. Next, as shown in FIG. 1(f), polysilicon 4. When Si♂N42 is removed, a flat structure in which an insulating film is buried in the element isolation region is obtained.

In this example, a CVD5iaNa film was used as a mask for silicon etching, but a thermal oxide film, a CVD5
An iOz film, a polysilicon film, or a multilayer film of the above films can also be used. Also, CVD SiOz
Polysilicon was used as a film for detecting the end point on a.
CVD5iaNa etc. can also be used.

According to this embodiment, the surface can be easily flattened.

Since the etching of the insulating film can be stopped at a required height with good control, an element isolation structure in which the insulating material is flatly embedded can be easily obtained with good reproducibility. Further, according to this embodiment, by providing the 5isN+ film 2, the element isolation region can be raised more than the element formation region, and the substrate can be prevented from being exposed due to cleaning or the like.

FIG. 2 shows the present invention applied to an element isolation structure using deep grooves. First, as shown in FIG. 2(a), CV
Using the DSiNa film 2 as an etching mask,
First, the silicon substrate is etched by, for example, 4 μm.The substrate surface is thermally oxidized, and a 5iOz film 7 of, for example, 500 is deposited.Next, CVD 5iaN4 is deposited, for example, by 500, and the groove side surfaces are etched by anisotropic dry etching. Only in 5
Next, as shown in FIG. 2(b), polysilicon (polysilicon) 9, which allows a thick film to be deposited relatively easily and does not cause cracks, is used as a first embedding material to leave the iaNa film 8. □Deposition 5, Sara, Yu. VDSi. 2 film-10 is deposited. Next, as shown in FIG. 2(c), polysilicon 9 and CVD 5iOz are applied to the region where the groove width is wider than the groove depth.
Selective etching is performed so that 10 remains.

Next, as a second filling material, polysilicon 11 with a good filling shape is deposited, and the trench is filled with a resist 6 applied to make the surface flat. Next, the etching speed of the resist 6 and the polysilicon 11 is CV under the condition that is equal to
Etching is performed until D5iOzlo is exposed. At this time, since CVD5iOzlO becomes a film for end point detection,
The structure shown in FIG. 2(d) can be easily obtained.

Next, for example, polysilicon 10 and polysilicon 11 are
μm oxidizes. At this time, the 5iaNa film 8 and the 5iaNa
Since the film 2 serves as a mask, the element formation region is not oxidized and the 5iaNa film 2 is removed to obtain the structure shown in FIG. 2(e).

According to this embodiment, an element isolation structure using a deep element isolation layer, which is necessary for element isolation between bipolar transistors, etc., can be easily realized.

In this example, polysilicon was used as the first filling material, but as shown in FIG. A structure in which polysilicon 11 is buried can be easily realized, and the wiring capacitance can be reduced.

〔Effect of the invention〕

According to the present invention, planarization can be easily performed with good distribution. In addition, the film for end point detection is placed in the first part of the wide element isolation area.
By depositing it on the insulator, it is possible to stop the etching of the insulating film at the required position in a well-controlled manner, making it possible to easily and precisely flatten the element formation region and the element isolation region, and to ensure that the insulator is flat. The device isolation structure embedded in the device can be easily obtained with good reproducibility.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are cross-sectional structural diagrams showing one embodiment of the method of the present invention, and FIGS. 2(a) to (e) and 3 are diagrams showing other embodiments of the method of the present invention. FIG. 2 is a cross-sectional structural diagram showing an example. 1...Silicon substrate, 2...CVD Sia
Na[, 3...CVDSiOx film, 4...polysilicon film, 5...CVD5iOz film, 6-...resist, 7-8iO2 film, 8...5isNa film, 9...polysilicon film , 10...CVD5iOz film, 11...
・Polysilicon film, 12-3iOz film, 13 ・P S
G membrane.

Claims (1)

[Claims] 1. In an element isolation method that involves selectively etching an element isolation region of a semiconductor substrate to form a groove, and filling the groove flat with an insulator, after forming the groove, a first buried film is deposited in the groove. a step of selectively leaving the first buried film only in the region where the groove width is wide; a step of depositing a second buried film; a step of applying a fluid substance to flatten the surface;
A process of etching the fluid material and the second buried film at the same etching rate until the entire surface is flattened until the second buried film on the first buried film and the second buried film on the element formation region are etched. A method for manufacturing a semiconductor device, comprising: