JPS58169939A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a flat surface and to install a fine upper wiring thereon by a method wherein a conductive layer pattern with masking material retained thereon is covered with a film of SiO2 produced by plasma CVD with its graded part to be etched rapidly in an etching process and the resultant groove surrounding the conductive layer is filled by another insulating film. CONSTITUTION:On an Si substrate 30, a resist mask 32 is used to form an Al layer 31, whereon an SiO2 layer 33 is laid down by means of plasma CVD. When etching is done with a buffer HF solution, the SiO2 layer 33 forming the graded part is selectively, rapidly removed together with SiO2 film 34. The Al layer 31 now finds itself buried in an SiO2 film as thick as the Al layer 31 and surrounded with an unburied groove 36. An SiO2 film 37 is deposited by CVD to fill up the groove 36. A PMAH resist 38 is applied to the SiO2 film 37 to fill the tiny recess remaining thereon.A perfectly flat surface is obtained by a process wherein the SiO2 film 37 and the resist 38 are etched at the same speed and the SiO2 film 37 is partially removed. Installation of an Al wiring 39 on a flat surface ensures a wiring finely finished with high reliability.

Description

Detailed Description of the Invention [Technical field to which the invention pertains] The present invention relates to a method for manufacturing a semiconductor device, and in particular, when forming a conductive film of two or more layers, electrically insulating and separating the conductive film from the underlying conductive film. The present invention relates to a technique for forming an upper conductive film by flattening the surface of an insulating film formed for the purpose of forming a conductive film.

;Prior art and its problems J In order to increase the density and integration of semiconductor devices, it has become necessary to form multi-layer wiring for electrically connecting each element to achieve higher integration. Furthermore, in order to speed up signal transmission, it is necessary for VC wiring materials to have low resistance. However, when forming a low-resistance material, typically a metal material, on the uneven surface of the wiring V, there are the following problems.6 First, the wiring material formed on the uneven surface has the following problems. The difference part is thinner than the flat part, and the wiring resistance is -F.
The reliability of the wiring is significantly reduced due to cracks or breaks in the wiring.

Next, when wiring is processed using ordinary ring graphing technology, if the surface is uneven, the lithography quality deteriorates and fine processing of the wiring cannot be performed.

Therefore, when processing the E wiring material, it is preferable in 4.C that the surface of the underlying insulating film be flat.

Conventionally, the following techniques have been used as the flattening technique and I7.

As shown in 11th Δfa), the first conductive film 2 is formed on the semiconductor substrate 1F. In addition, there is an insulating film 3 and a film 1 that melts during high temperature treatment, typically PSG'm or BPSGl.
Deposit ll[4. Next, as shown in figure (b), when high temperature treatment is typically performed at 1000° for 0.30 minutes, the melting film 4
When the film melts from 1 to 1, the film becomes a fluid film, so the steps on the surface become gentle. Thereafter, a second conductive film 5 is formed on the smooth surface as shown in FIG.

[7 or 12] Since this method requires high-temperature treatment, there is a problem in that low melting point wiring materials such as Ae and some silicide compounds cannot be used with the first conductive film 2.

Furthermore, such high-temperature treatment is not preferred because it also leads to deterioration of the air characteristics of the active elements of the semiconductor device.

Therefore, there is a method of applying a fluid film at room temperature to flatten the surface, as described below. That is, as shown in FIG. #L2, a first conductive pA 12 is formed on the semiconductor substrate 10, and an insulating film 12 is deposited thereon. Further, when a fluid film, typically a polymer film 13, is applied, the surface becomes smooth or flat.

Next, as shown in FIG. lb1, at least a portion of the polymer film 13 and the insulating film are etched under etching conditions such that the polymer film 13 and the insulating film 12 have the same etching rate.

In this case, it is preferable to use an anisotropic dry etching technique in order to obtain a smooth surface. Next, as shown in figure tc1, the insulating film 1 is
4 is added, and a second conductive film 15 is formed on that F.

However, with this method, it is difficult to make the surface flat using only the fluid film. 1!11 As shown in FIG. 3, due to the pattern shape of the first conductive material 21 on the lower side, surface irregularities remain, although they are gentle.

Such surface irregularities are not suitable for fine kneading C of the upper layer @2 conductive film 23, and the reliability of the wiring is also reduced.

[Purpose of the invention]

The present invention was made in view of the drawbacks of the conventional method, and it is possible to flatten the surface of the insulating film of the first conductive film-F in the lower layer, and to perform microfabrication of the second conductive film in the upper layer. The purpose is to improve wiring reliability.

[Summary of the invention]

In the present invention, after forming the first conductive film.

The first tetraelectric film is prepared using a two-step method as follows.
! , and the insulating film surface is covered with a marginal film so that the surface of the insulating film is almost flat.

That is, the mask material used for patterning the first conductive film is left on the first conductive film, and then the first insulating film is immediately coated on the entire surface with the same thickness as the first conductive film. It accumulates to a certain extent or more. As the tenth edge supply film, a film is used which has a property that the portion deposited on the stepped side wall portion is etched more quickly than the flat portion. Such a summons span 5 in 2 Th plasma sin,
Q is known. Thereafter, the insulating film deposited on the step portion by the mask material and the @1 conductive film is removed by etching using the first property of the first insulating film. after that,
When the mask material is removed, an empty groove having a constant V-shaped cross section is left around the first conductive film, and the first conductive film is removed.
The space between 114I and 114I is filled with the first insulating film.

Next, a 20th insulating film is deposited so as to fill the V-shaped trench to make the surface flat.

In this case, the surface on which the second insulating film is deposited has a constant V
Since there are small depressions due to the shape of the groove, the surface is flattened by the deposition of the insulating film. After applying the film, the surface is completely flattened using anisotropic dry etching technology, and a part of the fluid film and the second insulating film are etched in the same etching chamber to flatten the first surface. I don't mind if you try to make it your own.

[Effects of the invention] 4. By using the two-step insulating film forming method according to the method of the present invention, a high temperature heat treatment process is used.・The substantially flat insulating film surface without backing is made into a first conductive layer*, It can be formed into h. In addition, uniform flattening can be achieved regardless of the distance between the first conductive films. For this reason, it becomes possible to use materials with low melting points and low resistance, such as Ag and some silicide compounds, for the first conductive film in lower part 1-! It has also become possible to suppress the deterioration of the electrical characteristics of the device due to the above-mentioned high-temperature thermal process.

In addition, since it is possible to obtain a substantially flat surface,
The lithography precision for processing the second east conductive film to be formed thereafter was significantly improved, and microfabrication became easier.

Since there is no step difference, there is no need to worry about step breaks in conventional wiring, and the reliability of the wiring made of the second conductive film is significantly improved.

[Example 1 of the invention] Hereinafter, this invention will be applied to a first conductive film and a second conductive film.
An example will be explained regarding the case where a membrane is used.

FIG. 4(a) [As shown in FIG. An insulating film 1, such as a plasma CVD 8i01 film, is deposited on. The insulating film 1 may be any film as long as the part deposited on the stepped part is etched more quickly than the flat part.

Plasma CVD 8i0° film, sputter sto, -, plasma CVD 8x N4LPCVDPEG l[-
t'4Jl.

Next, as shown in FIG. 3C, the insulating film 1 at the stepped portion consisting of the resist mask 32 and the KL film 31 is etched away using the above properties of the insulating film 1. If the entire surface is etched, the side walls of the step will be quickly etched (the shape will be as shown in Figure C1). For example, if one grade of etching is performed with a buffered hydrofluoric acid solution, the plasma CVD 8i0 film on the upper step will be completely removed. As shown in the zero-order +dJ diagram, when the resist mask 32 is etched away by, for example, oxygen plasma treatment, the electric plasma CvDSi deposited on it is removed.
The O, film 34 was also removed at the same time, and a plasma CVD 8i0. embedded in the membrane. Next (as shown in Figure 511, an insulating film 2 is again deposited on the entire surface).
Typically, when CVD5iO, film 3] is deposited, the above V
The letter-shaped groove is filled in and CVD8i0. A small recess remains on the surface of the membrane 37. Therefore, the surface was etched under conditions that the etching speed of the fluid AH resist and the insulating film 2 were equal.
When the MAH resist and at least a portion of the insulating film 2 are removed by etching, the surface of the insulating film 2 becomes completely flat. Also CVD8i0. If the film 37 is formed sufficiently thick, cvnst
o. The surface of the film 37 is substantially flat, and in this case, subsequent resist application and dry etching are unnecessary. CVD8i0. After the surface of the film 37 is flattened by the above method, an oxide film can be further deposited to obtain a desired insulating film thickness.

Thereafter, as shown in FIG. tf1, an upper film 39 is formed on the surface of the flat insulating film. According to this example, since the surface of the lower layer film can be almost completely covered with a flat insulating film, fine processing of the upper layer AJ film is possible, and the reliability of the interconnection is significantly improved. did.

Although this example describes a two-layer structure of KL film as the wiring material, other wiring materials such as silicide compounds,
The impurity-doped poly-8i and high melting point metal may be used as the first conductive film, and may be applied to the second conductive film.
Also, 1st. Both the second conductive film may be an AJ or AI compound film, and the present invention can also be applied to a structure of three or more layers.

[Brief explanation of drawings]

Figure 1 (a) - (cl), Figure 2 (a) -' (c)
and Fig. 3 is a cross-sectional view of the manufacturing process for explaining the technique of flattening the surface of the interlayer insulating film by the conventional method, and Fig. 4) to (f)
FIG. 2 is a manufacturing process sectional view for explaining the present invention in detail. In the figure, 1.10, 20.30... semiconductor substrate 2.5, 11
, 15, 21.23.31.39... Conductive film 3.
12, 14, 22. 37... Interlayer insulating film 4...
Insulating films 13, 38 that melt at high temperatures Fluid film 32... Mask material 33.34.35"7' 5 Sma CVD 5ins
9% 36...V-shaped empty ditch agent Patent attorney Chika Nori; Kensuke (1 other person) 1st
Figure 3 Figure 4-

Claims (1)

Scope of Claims (11) A step of depositing a first conductive film on a semiconductor substrate, forming a mask pattern on the first conductive film, and using this mask to apply the first conductive film to the semiconductor substrate. a step of etching the step sidewall, a step of depositing a first insulating film having a property of quickly etching the step sidewall, and etching the entire surface to remove the step sidewall and the barrier film; Manufacture of a semiconductor device characterized by the step of removing a first insulating film together with a first insulating film, depositing a second insulating film on the entire surface, and further forming a second conductive film thereon. Method. (2) The first insulating film is a plasma CVI)Sin film,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the film is an i3N4 film or an LPGVDPEG film. (3) The first conductive film has impurities introduced into it.
poly8i Ill. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the second conductive film is a silicide film or a high melting metal film, and the second conductive film is a film made of Ag or Al compound. (4) A dipping method for a semiconductor device according to claim 1, wherein the first conductive film and the second conductive film are Al films made of an Al compound. (5) After etching the surface of the second insulating film, a third insulating film is deposited on the surface to obtain a desired thickness of the insulating film. A method for manufacturing a semiconductor device.