JPH0744174B2 - Etching method - Google Patents
Etching methodInfo
- Publication number
- JPH0744174B2 JPH0744174B2 JP2408587A JP2408587A JPH0744174B2 JP H0744174 B2 JPH0744174 B2 JP H0744174B2 JP 2408587 A JP2408587 A JP 2408587A JP 2408587 A JP2408587 A JP 2408587A JP H0744174 B2 JPH0744174 B2 JP H0744174B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- etching
- film
- silicon
- end point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は高密度集積回路に要する精密エッチング方法に
関するものである。Description: FIELD OF THE INVENTION The present invention relates to a precision etching method required for high density integrated circuits.
従来の技術 従来、溝掘り酸化膜埋め込み形分離、いわゆるBOX分離
工程はLOCOS分離に代わる分離方式として注目されてい
る。これはシリコン基板の分離領域をエッチングし、CV
D法でシリコン酸化膜を堆積し平坦化エッチバック工程
を程てシリコン溝にのみシリコン酸化膜を残す方法であ
る。2. Description of the Related Art Conventionally, the so-called BOX separation process, which is a grooving oxide film embedded type separation process, has been attracting attention as an alternative separation method to LOCOS separation. This etches the isolation area of the silicon substrate,
In this method, a silicon oxide film is deposited by the D method, and a flattening etchback process is performed to leave the silicon oxide film only in the silicon trench.
発明が解決しようとする問題点 従来の技術では平坦化工程で終点判定が時間エッチによ
るものである為、埋め込みシリコン酸化膜と能動領域の
Siの断差にばらつきが出て素子特性に悪影響を出してい
た。Problems to be Solved by the Invention In the conventional technique, since the end point determination is performed by time etching in the planarization process, the buried silicon oxide film and the active region are not
Variations in the Si gap were found to have a negative effect on device characteristics.
問題点を解決するための手段 本発明は上記問題点を解決するため、埋め込み酸化膜上
あるいはポリシリコン膜と埋め込み酸化膜の間にシリコ
ン窒化膜を堆積することにより、エッチバックの終点判
定をCNラジカルの発光スペクトルの強度変化によって行
うものである。Means for Solving the Problems In order to solve the above problems, the present invention determines the end point of etchback by depositing a silicon nitride film on a buried oxide film or between a polysilicon film and a buried oxide film. This is performed by changing the intensity of the emission spectrum of radicals.
作用 本発明により、エッチバックの終点判定が自動で行われ
るため、精密なエッチバックが再現性良く行える。Effect According to the present invention, since the end point of etch back is automatically determined, precise etch back can be performed with good reproducibility.
実施例 第1図に本発明の一実施例を示す。これを工程順に説明
する。半導体シリコン基板1上に熱酸化膜2を50nm堆積
しポリシリコン3を140nm堆積し、次にレジストパター
ンをつけてポリシリコン3,熱酸化膜2,シリコン基板1を
800nmエッチングし、基板1に段差10を形成する。次にL
PCVD法において埋め込み用のシリコン酸化膜4を1100nm
堆積し、続いて、後のエッチバック工程での終点検出用
のシリコン窒化膜5を100nm堆積する。次にレジストパ
ターン6を990nmの高さでつけて続いてスパッタ法でシ
リコン酸化膜7を20nm形成する。続いてレジストコート
してレジスト8を形成する。このようにして出来た膜を
エッチバック法でエッチングする。すなわちレジスト8
をO2を含むガスでドライエッチングする。そして酸化膜
7以下をCHF3,C2F6,O2の混合ガスでエッチングする。第
2図は第1図yの位置までエッチングした状態を示す。Embodiment FIG. 1 shows an embodiment of the present invention. This will be described in the order of steps. A thermal oxide film 2 is deposited to a thickness of 50 nm and a polysilicon 3 is deposited to a thickness of 140 nm on a semiconductor silicon substrate 1, and then a resist pattern is applied to the polysilicon 3, the thermal oxide film 2 and the silicon substrate 1.
800 nm is etched to form a step 10 on the substrate 1. Then L
The silicon oxide film 4 for embedding in the PCVD method is 1100 nm
After the deposition, the silicon nitride film 5 for detecting the end point in the subsequent etch back process is deposited to 100 nm. Next, a resist pattern 6 is applied at a height of 990 nm, and subsequently a silicon oxide film 7 is formed to a thickness of 20 nm by a sputtering method. Subsequently, resist coating is performed to form a resist 8. The film thus formed is etched by the etch back method. That is, the resist 8
Is dry-etched with a gas containing O 2 . Then, the oxide film 7 and below are etched with a mixed gas of CHF 3 , C 2 F 6 and O 2 . FIG. 2 shows a state of being etched to the position shown in FIG.
次にポリシリコン3を除去し、SiO22を50nmエッチング
すると第3図に示すごとく基板1の段差の低部(凹部)
に素子分離用の酸化膜4が埋め込み形成される。エッチ
バック工程でシリコン窒化膜5のエッチング時のCN*の
発光例えば387nmの波長の光の時間変化を見てゆくと第
4図のようになる。第4図のXのピークは第1図のXの
線部分のエッチング時、Yのピークは第1図のyのエッ
チング時である。この発光を読みながらエッチングして
2つ目のピークが終った所でエッチング終了判定すれば
正確にエッチバックが行える。Next, the polysilicon 3 is removed, and SiO 2 2 is etched to a thickness of 50 nm. Then, as shown in FIG.
An oxide film 4 for element isolation is embedded and formed therein. FIG. 4 shows the change over time of CN * emission, for example, light having a wavelength of 387 nm when the silicon nitride film 5 is etched in the etch back process. The peak of X in FIG. 4 is during the etching of the line portion of X in FIG. 1, and the peak of Y is during the etching of y in FIG. If etching is performed while reading this emission and the etching end is judged when the second peak ends, accurate etching back can be performed.
次に、本発明の他の実施例を第5〜第8図とともに説明
する。第5図において、第1図と同一部分には同一番号
を付す。Next, another embodiment of the present invention will be described with reference to FIGS. 5, the same parts as those in FIG. 1 are designated by the same reference numerals.
シリコン基板1上に熱酸化膜2を50nm堆積し、次にポリ
シリコン3を140nm、さらに終点検出用のシリコン窒化
膜5を100nm堆積する。この実施例ではポリシリコン3
の上に終点検出用の窒化膜5を形成する。次にレジスト
パターンをつけてシリコン窒化膜5(100nm)、ポリシ
リコン3(140nm)、熱酸化膜2(50nm)、シリコン基
板1を800nmエッチングして段差10を形成する。次にLPC
VD法によってシリコン酸化膜4を1100nm堆積する。次に
レジストパターン6を1090nmつけた後、続いてシリコン
酸化膜7をスパッタ法で20nm堆積する。さらにレジスト
8をコートして平坦な面とする。次にこの膜を前述した
と同様のガスを用いてエッチバック法でエッチングする
と第6図のようになる。続いてポリシリコン3を除去
し、熱酸化膜2(50nm)をエッチングした状態を第7図
に示す。A thermal oxide film 2 is deposited to a thickness of 50 nm on a silicon substrate 1, a polysilicon 3 is deposited to a thickness of 140 nm, and a silicon nitride film 5 for detecting an end point is deposited to a thickness of 100 nm. In this embodiment, polysilicon 3
A nitride film 5 for detecting the end point is formed thereon. Next, a resist pattern is formed and the silicon nitride film 5 (100 nm), polysilicon 3 (140 nm), thermal oxide film 2 (50 nm) and silicon substrate 1 are etched by 800 nm to form a step 10. Then LPC
A silicon oxide film 4 is deposited to a thickness of 1100 nm by the VD method. Next, after forming a resist pattern 6 of 1090 nm, a silicon oxide film 7 is subsequently deposited to a thickness of 20 nm by a sputtering method. Further, the resist 8 is coated to form a flat surface. Next, this film is etched by the etch-back method using the same gas as described above, as shown in FIG. Subsequently, the state in which the polysilicon 3 is removed and the thermal oxide film 2 (50 nm) is etched is shown in FIG.
エッチバック工程での終点検出用に用いる、シリコン窒
化膜のエッチング時に発生するCNラジカルの発光強度の
時間変化を第8図に示す。第8図のピークは窒化膜5の
エッチング時を示す。シリコン窒化膜5のエッチングに
よって生じたCNラジカルの発光強度のピークが終った時
点を終点として精密なエッチバックが可能となる。FIG. 8 shows the time change of the emission intensity of CN radicals generated during the etching of the silicon nitride film, which is used for detecting the end point in the etchback process. The peak in FIG. 8 indicates the time when the nitride film 5 is etched. Precise etch back is possible with the end point at the peak of the emission intensity of the CN radical generated by the etching of the silicon nitride film 5.
発明の効果 本発明により、エッチバック工程におけるエッチングの
終点検出を正確に制度良く行うことができ、微細パター
ンを有する集積回路に要するエッチバック工程が精密に
再現性よく自動的に行われるため、高密度な半導体装置
の製造歩留り向上に大きく寄与するものである。EFFECTS OF THE INVENTION According to the present invention, it is possible to accurately and accurately detect the end point of etching in the etchback process, and the etchback process required for an integrated circuit having a fine pattern is automatically performed with high precision and reproducibility. This greatly contributes to the improvement of the manufacturing yield of dense semiconductor devices.
第1図,第5図は本発明の実施例のエッチバック前の半
導体基板の断面図、第2図,第6図はエッチバック後の
断面図、第3図,第7図は分離終了後の断面図、第4
図,第8図はエッチバック中のCNラジカルの発光強度の
時間変化を示す図である。 1……シリコン基板、2……熱酸化膜、3……ポリシリ
コン、4……シリコン酸化膜、5……シリコン窒化膜、
6……レジスト、7……シリコン酸化膜、8……レジス
ト。1 and 5 are sectional views of a semiconductor substrate before etching back according to an embodiment of the present invention, FIGS. 2 and 6 are sectional views after etching back, and FIGS. 3 and 7 are after separation. Sectional view of the fourth
FIG. 8 and FIG. 8 are views showing the change over time in the emission intensity of CN radicals during etchback. 1 ... Silicon substrate, 2 ... Thermal oxide film, 3 ... Polysilicon, 4 ... Silicon oxide film, 5 ... Silicon nitride film,
6 ... resist, 7 ... silicon oxide film, 8 ... resist.
Claims (2)
積する工程と、上記酸化膜上にシリンコン窒化膜を堆積
する工程と、レジストをコートして表面を平坦化する工
程と、上記工程で作られた膜をエッチングするとともに
CNラジカルの発光強度をモニタし上記エッチングの終点
検出することを特徴とするエッチング方法。1. A step of depositing a silicon oxide film on a substrate having steps, a step of depositing a silicon nitride film on the oxide film, a step of coating a resist to planarize the surface, and While etching the formed film
An etching method characterized by monitoring the emission intensity of CN radicals to detect the end point of the etching.
シリコン窒化膜を堆積する工程と、上記窒化膜上にシリ
コン酸化膜を堆積する工程と、レジストをコートして表
面を平坦化する工程と、上記工程で作られた膜をエッチ
ングしCNラジカルの発光強度をモニタし終点検出するこ
とを特徴とするエッチング方法。2. A step of depositing a silicon nitride film on a polysilicon film on a substrate having a step, a step of depositing a silicon oxide film on the nitride film, and a resist coating to planarize the surface. An etching method comprising the steps, and etching the film formed in the above step to monitor the emission intensity of CN radicals to detect the end point.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2408587A JPH0744174B2 (en) | 1987-02-04 | 1987-02-04 | Etching method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2408587A JPH0744174B2 (en) | 1987-02-04 | 1987-02-04 | Etching method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63192236A JPS63192236A (en) | 1988-08-09 |
JPH0744174B2 true JPH0744174B2 (en) | 1995-05-15 |
Family
ID=12128560
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2408587A Expired - Lifetime JPH0744174B2 (en) | 1987-02-04 | 1987-02-04 | Etching method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0744174B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2692199B2 (en) * | 1988-11-19 | 1997-12-17 | 富士通株式会社 | Etching end point detector |
JP5258121B2 (en) * | 2008-02-08 | 2013-08-07 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor manufacturing method |
WO2009098778A1 (en) * | 2008-02-08 | 2009-08-13 | Unisantis Electronics (Japan) Ltd. | Semiconductor manufactiring method |
US8026141B2 (en) | 2008-02-08 | 2011-09-27 | Unisantis Electronics (Japan) Ltd. | Method of producing semiconductor |
JP5471630B2 (en) * | 2010-03-10 | 2014-04-16 | 凸版印刷株式会社 | Method for manufacturing mask for extreme ultraviolet exposure |
-
1987
- 1987-02-04 JP JP2408587A patent/JPH0744174B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS63192236A (en) | 1988-08-09 |
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