KR960005566B1 - Method for forming a charge storage electrode - Google Patents

Method for forming a charge storage electrode Download PDF

Info

Publication number
KR960005566B1
KR960005566B1 KR1019920020581A KR920020581A KR960005566B1 KR 960005566 B1 KR960005566 B1 KR 960005566B1 KR 1019920020581 A KR1019920020581 A KR 1019920020581A KR 920020581 A KR920020581 A KR 920020581A KR 960005566 B1 KR960005566 B1 KR 960005566B1
Authority
KR
South Korea
Prior art keywords
forming
polysilicon
storage electrode
etching
photoresist pattern
Prior art date
Application number
KR1019920020581A
Other languages
Korean (ko)
Other versions
KR940012605A (en
Inventor
박영진
이석규
송대식
Original Assignee
현대전자산업주식회사
김주용
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 현대전자산업주식회사, 김주용 filed Critical 현대전자산업주식회사
Priority to KR1019920020581A priority Critical patent/KR960005566B1/en
Publication of KR940012605A publication Critical patent/KR940012605A/en
Application granted granted Critical
Publication of KR960005566B1 publication Critical patent/KR960005566B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Abstract

forming a storage node contact hole(2) and burying this contact hole with a first polyslilicon(3); forming a photoresist pattern on a storage node; forming an LTO layer(11) on the resulting structure and etching back it to expose the photoresist pattern; removing the exposed photoresist pattern to form a groove(5) in which a cylindrical storage node will be formed, depositing a second polysilicon(3A) on the resulting structure, coating the second polysilicon layer with a photoresist and etching back it to expose the second polysilicon layer; etching the exposed portion of the second polysilicon layer to form cylindrical second polysilicon pattern; and wet-etching the LTO layer(11), thereby forming the cylindrical storage node composed of the first and second polysilicon layers.

Description

전하 저장 전극 형성방법How to form charge storage electrode

제1도는 실린더 구조를 갖는 전하 저장 전극의 단면사시도.1 is a cross-sectional perspective view of a charge storage electrode having a cylindrical structure.

제2(a)도 내지 제2(f)도는 종래 방법에 의해 전하 저장 전극을 형성하는 단계를 도시한 단면도.2 (a) to 2 (f) are cross-sectional views showing the steps of forming the charge storage electrode by the conventional method.

제3(a)도 내지 제3(f)도는 본 발명에 의해 전하 저장 전극을 형성하는 단계를 도시한 단면도.3 (a) to 3 (f) are cross-sectional views showing the steps of forming a charge storage electrode according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 2 : 저장전극 콘택홀1: silicon substrate 2: storage electrode contact hole

3 : 1차 폴리실리콘 3A : 2차 폴리실리콘3: primary polysilicon 3A: secondary polysilicon

3B : 2차 폴리실리콘 패턴 4 : 옥사이드막3B: secondary polysilicon pattern 4: oxide film

5 : 홈 7, 12 : 실린더 구조의 저장전극5: groove 7, 12: cylinder electrode

8, 9 : 감광막 9A : 감광막 패턴8, 9: photosensitive film 9A: photosensitive film pattern

11 : 저온 옥사이드막 13 : 하부절연막11 low temperature oxide film 13 lower insulating film

본 발명은 반도체 소자의 전하저장전극(이하, 저장전극이라 한다) 형성에 관한 것으로서, 특히 실린더 구조를 갖는 저장전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the formation of charge storage electrodes (hereinafter referred to as storage electrodes) in semiconductor devices, and more particularly to a method of forming storage electrodes having a cylinder structure.

기존의 평탄형 캐패시터에서는 저장전극과 플래이트간의 캐패시터 유효면적이 좁아서 큰 용량의 캐패시터를 얻기가 어려우나, 캐패시터의 저장전극형성에 실린더 구조(제 1 도 참조)를 도입하게 되면 저장전극과 플래이트 간의 캐패시터 유효 면적이 증가하여 용량의 증대를 도모할 수 있다.In the conventional flat capacitor, the effective area of the capacitor between the storage electrode and the plate is narrow, so that it is difficult to obtain a large capacity capacitor.However, when a cylinder structure (see FIG. 1) is introduced to form the storage electrode of the capacitor, the capacitor between the storage electrode and the plate becomes effective. The area can be increased and the capacity can be increased.

살린더 구조의 저장전극을 형성하는데 있어서, 종래의 방법을 제2(a)도 내지 제2(f)도를 참조하여 설명하고자 한다.In forming a storage electrode having a salad structure, a conventional method will be described with reference to FIGS. 2 (a) to 2 (f).

제2(a)도는 실리콘 기판(1)상에 하부절연막(13)을 형성하고 소정 부분의 하부절연막(13)을 제거하여 저장 전극 콘택홀(2)을 형성한 후, 1차 폴리실리콘(3)을 매립한 것을 나타낸 단면도이다.In FIG. 2A, after forming the lower insulating layer 13 on the silicon substrate 1 and removing the lower insulating layer 13 of the predetermined portion to form the storage electrode contact hole 2, the primary polysilicon 3 is formed. It is sectional drawing which shows that embedding).

제2(b)도는 제2(a)도의 전체 상부에 옥사이드막(4)을 증착시킨 단면도이다. 옥사이드막(4)을 증착시킬 때, 하부에 단차가 존재하게 되면 옥사이드막을 평탄하게 증착시키기가 어렵다는 단점이 존재하게 된다.FIG. 2 (b) is a sectional view in which the oxide film 4 is deposited on the entire top of FIG. 2 (a). When depositing the oxide film 4, there is a disadvantage that it is difficult to deposit the oxide film evenly if there is a step below.

제2(c)도는 실린더 구조를 형성하기 위해 증착된 옥사이드막(4)의 일정 부분을 식각하여 홈(5)을 만든 단면도이다.FIG. 2 (c) is a cross-sectional view of the groove 5 formed by etching a portion of the oxide film 4 deposited to form a cylinder structure.

제2(d)도는 제2(c)도의 전체 상부의 표면을 따라 2차 폴리실리콘(3A)을 도포한 단면도이다.FIG. 2 (d) is sectional drawing which apply | coated secondary polysilicon 3A along the surface of the whole upper part of FIG. 2 (c).

제2(e)도는 제2(d)도의 상부 표면을 따라 감광막(8)을 도포한 후, 2차 폴리실리콘(3A) 상부면까지 감광막(8)을 에치백(etch back)한 다음, 노출된 2차 폴리실리콘(3A)을 식각하여 인접한 저장전극간의 1차 폴리실리콘(3)과 접속된 실린더 구조의 2차 폴리실리콘 패턴(3B)을 형성한 단면도이다.FIG. 2 (e) shows the photoresist film 8 along the upper surface of FIG. 2d, and then etches back the photoresist film 8 to the upper surface of the secondary polysilicon 3A. The secondary polysilicon 3A is etched to form a secondary polysilicon pattern 3B having a cylindrical structure connected to the primary polysilicon 3 between adjacent storage electrodes.

제2(f)도는 실린더 구조의 2차 폴리실리콘 패턴(3B) 주위의 옥사이드막(4)을 습식식각하여 실린더 구조의 저장전극(7)을 형성한 단면도이다.FIG. 2 (f) is a cross-sectional view of the cylindrical storage electrode 7 formed by wet etching the oxide film 4 around the secondary polysilicon pattern 3B.

상기의 공정단계로 저장전극을 형성할 경우, 제2(b)도의 옥사이드막을 증착함에 있어 하부 단차에 의해 평탄한 옥사이드막을 형성하기가 힘들고, 실린더 구조의 높이에 따라 옥사이드막의 두께를 조정하여 증착시키기가 까다롭다.When the storage electrode is formed in the above process step, it is difficult to form a flat oxide film due to the lower step in depositing the oxide film of FIG. 2 (b), and to deposit the oxide film by adjusting the thickness of the oxide film according to the height of the cylinder structure. Picky.

따라서 이러한 문제를 해결할 수 있는 안정된 구조의 실린더 저장전극을 형성하는 방법을 제공하는 것이 본 발명의 목적이다.Therefore, it is an object of the present invention to provide a method for forming a cylinder storage electrode having a stable structure that can solve this problem.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제3(a)도 내지 제3(f)도는 본 발명의 제 1 실시에에 의해 저장전극을 형성하는 단계를 도시한 것이다.3 (a) to 3 (f) illustrate the steps of forming the storage electrode according to the first embodiment of the present invention.

제3(a)도는 실리콘기판(1) 상에 하부절연막(13)을 형성하고, 일정부분의 하부절연막(13)을 식각하여 저장전극 콘택홀(2)을 형성한 후, 1차 폴리실리콘(3)을 매립한 단면도이다.In FIG. 3 (a), the lower insulating layer 13 is formed on the silicon substrate 1, and a portion of the lower insulating layer 13 is etched to form the storage electrode contact hole 2, and then the primary polysilicon ( 3) It is a sectional view which buried.

제3(b)도는 제3(a)도의 전체구조 상부에 감광막(9)을 도포한 후, 노광, 현상공정으로 실린더 구조의 저장전극이 형성될 부분에만 감광막 패턴(9A)을 형성한 단면도이다.FIG. 3 (b) is a cross-sectional view of the photosensitive film 9 formed on the entire structure of FIG. .

제3(c)도는 제3(b)도의 전체구조 상부에 감광막과 함께 사용할 수 있는 저온 옥사이드(11) 예를들어, SOG 또는 PECVD옥사이드 등을 일정 두께만큼 도포한 후, 상기 저온 옥사이드(11)를 에치백하여 감광막 패턴(9A)의 표면이 노출되기까지 식각한 상태를 나타낸 단면도이다.3 (c) is a low-temperature oxide (11) that can be used with a photoresist film on the entire structure of Figure 3 (b), for example, SOG or PECVD oxide after applying a predetermined thickness, the low-temperature oxide (11) Is a cross-sectional view showing a state where the back surface is etched until the surface of the photosensitive film pattern 9A is exposed.

제3(d)도는 제3(c)도의 노출된 감광막 패탄(9A)을 제거하고 전체 상부의 표면을 따라 2차 폴리실리콘(3A)은 도포한 단면도이다.FIG. 3 (d) is a cross-sectional view of the exposed photoresist shell 9A of FIG.

제3(e)도는 제3(d)도의 상부에 감광막(8)을 도포한 후, 감광막(8)을 2차 폴리실리콘(3A) 상부면이 노출되기까지 에치백한 다음, 노출된 2차 폴리실리콘(3A)을 시각하여 1차 폴리실리콘(3)에 접속된 실린더 구조를 갖는 2차 폴리실리콘 패턴(3B)을 형성한 상태를 나타낸 단면도이다.After applying the photoresist film 8 to the upper part of FIG. 3 (e) or FIG. 3 (d), the photoresist film 8 is etched back until the upper surface of the secondary polysilicon 3A is exposed, and then the exposed secondary It is sectional drawing which showed the state which formed the secondary polysilicon pattern 3B which has the cylinder structure connected to the primary polysilicon 3 by viewing polysilicon 3A.

제3(f)도는 저온 옥사이드(11)을 습식식각하여 실린더 구조의 저장전극(12)을 형성한 단면도이다.3 (f) is a cross-sectional view of the storage electrode 12 having a cylindrical structure by wet etching the low-temperature oxide 11.

본 발명의 제 2 실시예(도시안됨)는 제 1 실시예의 제3(f)도에서 저온 옥사이드를 습식식각할 때, 저온 옥사이드(11)와 그 하부에 위치한 하부절연막(13)과의 에치 선택비가 작을 경우는, 제3(a)도의 전체구조 상부에 일정 두께의 질화막을 도포하고 제3(b)도~제3(c)도의 공정을 진행한 후, 감광막 패턴(9A)을 제거하고, 노출되는 절화막을 식각함으로써 2차 폴리실리콘(3A)이 1차 폴리실리콘(3)에 콘택되도록 하면 된다.The second embodiment of the present invention (not shown) selects the etch between the low temperature oxide 11 and the lower insulating layer 13 disposed below when the low temperature oxide is wet etched in FIG. 3 (f) of the first embodiment. If the ratio is small, a nitride film having a predetermined thickness is applied on the entire structure of FIG. 3 (a), the processes of FIGS. 3 (b) to 3 (c) are performed, and then the photosensitive film pattern 9A is removed. The secondary polysilicon 3A may be contacted with the primary polysilicon 3 by etching the exposed cut film.

그 다음 단계로 제3(d)도~제3(f)도의 순서로 진행함으로써 본 발명의 제 1 실시예와 동일한 결과를 얻을 수 있다.In the next step, the same results as in the first embodiment of the present invention can be obtained by proceeding in the order of FIGS. 3 (d) to 3 (f).

상기한 본 발명의 제 1 실시예 또는 제 2 실시예의 방법으로 저장전극을 형성하게 되면, 두꺼운 옥사이드막을 도포하고 에치하는 공정 등을 생략할 수 있으며, 저온 옥사이드로 SOG를 사용할 경우 포토 작업만으로 실린더 구조를 형성할 수 있는 단순한 공정이 된다.When the storage electrode is formed by the method of the first or second embodiment of the present invention described above, a process of applying and etching a thick oxide film may be omitted. It is a simple process to form a structure.

또한, 감광막의 두께에 따라 실린더의 높이를 조정할 수 있으며, 실린더가 형성된 부분의 아랫면에 단차가 존재해도 포토작업으로 감광막을 평탄하게 도포하면 실린더 구조를 쉽게 형성할 수 있으므로, 복잡한 토폴로지에서도 실린더 구조를 용이하게 형성할 수 있다.In addition, the height of the cylinder can be adjusted according to the thickness of the photoresist film, and even if there is a step on the lower surface of the cylinder formed portion, it is possible to easily form the cylinder structure by applying the photoresist film flatly by photo work. It can be formed easily.

Claims (3)

반도체 소자의 전하저장전극 형성에 있어서, 저장전극 콘택홀을 형성한 후 이 저장전극 콘택홀에 1차 폴리실리콘을 매립하는 단계와, 저장전극이 형성될 부분에만 감광막 패턴을 형성하는 단계와, 전체구조 상부에 저온 옥사이드를 도포한 후 에치백하여 감광막 패턴의 상부면이 노출되게 하는 단계와, 노출된 감광막 패턴을 제거하여 실린더 구조의 저장전극의 형성할 홈을 형성하는 단계와, 전체구조 상부에 일정 두께의 2차 폴리실리콘을 도포하는 단계와, 2차 폴리실리콘 상부에 감광막을 도포한 후 2차 폴리실리콘의 상부면이 노출되기까지 에치백한 다음, 노출된 2차 폴리실리콘을 식각하여 실린더 구조의 2차 폴리실리콘 패턴을 형성하는 단계와, 저온 옥사이드를 습식식각하여 1차 폴리실리콘과 2차 폴리실리콘이 접속된 실린더 구조의 저장전극을 형성하는 단계로 이루어지는 것을 특징으로 하는 전하저장전극 형성방법.Forming charge storage electrodes of a semiconductor device, forming a storage electrode contact hole and then embedding primary polysilicon in the storage electrode contact hole, forming a photoresist pattern only on a portion where the storage electrode is to be formed, Applying a low temperature oxide on the structure and then etching back to expose the upper surface of the photoresist pattern; removing the exposed photoresist pattern to form a groove for forming a storage electrode of a cylinder structure; Applying a thickness of secondary polysilicon, applying a photoresist film on top of the secondary polysilicon, etching back until the upper surface of the secondary polysilicon is exposed, and then etching the exposed secondary polysilicon Forming a secondary polysilicon pattern having a structure; and a storage electrode having a cylindrical structure in which primary polysilicon and secondary polysilicon are connected by wet etching low temperature oxide. Forming a charge storage electrode, characterized in that comprising the step of forming. 제 1 항에 있어서, 상기 저온 옥사이드는 SOG 또는 PECVD 옥사이드로 형성하는 것을 특징으로 하는 전하저장전극 형성방법.The method of claim 1, wherein the low temperature oxide is formed of SOG or PECVD oxide. 제 1 항에 있어서, 저온 옥사이드와 그 하부에 위치한 하부절연막과의 식각 선택비가 작을 경우, 저장 전극 콘택홀에 1차 폴리실리콘을 매립한 다음, 정체구조 상부에 일정두께의 질화막을 도포한 다음, 상기와 같은 공정으로 감광막 패턴을 형성하고, 저온 옥사이드를 형성한 후, 감광막 패턴을 제거하고 노출되는 질화막을 식각한 다음, 2차 폴리실리콘을 도포하는 단계를 포함하는 것을 특징으로 하는 전하저장전극 형성방법.The method of claim 1, wherein when the etching selectivity between the low-temperature oxide and the lower insulating layer disposed below the first layer is small, the first polysilicon is buried in the storage electrode contact hole, and then a nitride film having a predetermined thickness is applied on the top of the stagnant structure. Forming a photoresist pattern, forming a low-temperature oxide, removing the photoresist pattern, etching the exposed nitride film, and then applying a secondary polysilicon to form a charge storage electrode. Way.
KR1019920020581A 1992-11-04 1992-11-04 Method for forming a charge storage electrode KR960005566B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920020581A KR960005566B1 (en) 1992-11-04 1992-11-04 Method for forming a charge storage electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920020581A KR960005566B1 (en) 1992-11-04 1992-11-04 Method for forming a charge storage electrode

Publications (2)

Publication Number Publication Date
KR940012605A KR940012605A (en) 1994-06-24
KR960005566B1 true KR960005566B1 (en) 1996-04-26

Family

ID=19342459

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920020581A KR960005566B1 (en) 1992-11-04 1992-11-04 Method for forming a charge storage electrode

Country Status (1)

Country Link
KR (1) KR960005566B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001313379A (en) * 2000-04-28 2001-11-09 Nec Corp Manufacturing method of semiconductor memory, and manufacturing method of capacitive element

Also Published As

Publication number Publication date
KR940012605A (en) 1994-06-24

Similar Documents

Publication Publication Date Title
KR960011652B1 (en) Stack capacitor and the method
KR100200022B1 (en) Process of fabricating semiconductor ic device having small geometry contact by using spacer on photoresist mask
KR100199351B1 (en) Method for forming stack capacitor of semiconductor device
KR960001336B1 (en) Method of manufacturing a semiconductor memory device
KR960005566B1 (en) Method for forming a charge storage electrode
KR0146246B1 (en) Method for manufacturing semiconductor device contact
KR970000222B1 (en) Method for manufacturing dram cell capacitor
KR940004779A (en) Device isolation region formation method of semiconductor device using trench technology
KR950000655B1 (en) Storage electrode manufacturing method of semiconductor device
KR960014728B1 (en) Method of formation of semiconductor with storage electrode
KR100218730B1 (en) Fabricating method of semiconductor device
KR100336770B1 (en) Capacitor forming method
KR0124576B1 (en) Capacitor apparatus of semiconductor memory
KR960001338B1 (en) Method of manufacturing storage node for semiconductor device
KR20030042232A (en) Method of forming mim capacitor having cylinder structure
KR0131731B1 (en) Manufacture of semiconductor device
KR100328824B1 (en) Manufacturing method for capacitor
KR100218338B1 (en) A cylinderical capacitor manufacturing method
KR100218727B1 (en) Forming method of contact hole of semiconductor device
KR910008123B1 (en) Semiconductor memory device having stacked capacitor and method of fabricating thereof
KR20010068729A (en) Manufacturing method for capacitor
KR100286336B1 (en) Manufacturing method for capacitor
KR0148326B1 (en) Fabrication method of semiconductor device
KR100258857B1 (en) Manufacturing method for isolation structure of semiconductor device
KR0165419B1 (en) Method of manufacturing cylindrical capacitor using spacer

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050318

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee