FR3081241B1 - Procede de gestion de la valeur de la tension d'alimentation d'un module d'un circuit integre, et circuit integre associe - Google Patents

Procede de gestion de la valeur de la tension d'alimentation d'un module d'un circuit integre, et circuit integre associe Download PDF

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Publication number
FR3081241B1
FR3081241B1 FR1854118A FR1854118A FR3081241B1 FR 3081241 B1 FR3081241 B1 FR 3081241B1 FR 1854118 A FR1854118 A FR 1854118A FR 1854118 A FR1854118 A FR 1854118A FR 3081241 B1 FR3081241 B1 FR 3081241B1
Authority
FR
France
Prior art keywords
integrated circuit
supply voltage
module
managing
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1854118A
Other languages
English (en)
Other versions
FR3081241A1 (fr
Inventor
Alexandre Sarafianos
Thomas Ordas
Yanis Linge
Jimmy Fort
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1854118A priority Critical patent/FR3081241B1/fr
Priority to US16/411,819 priority patent/US10949572B2/en
Publication of FR3081241A1 publication Critical patent/FR3081241A1/fr
Application granted granted Critical
Publication of FR3081241B1 publication Critical patent/FR3081241B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07363—Means for preventing undesired reading or writing from or onto record carriers by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Power Sources (AREA)
  • Electronic Switches (AREA)

Abstract

Procédé de gestion de la tension d'alimentation d'un module d'un circuit intégré (CI), dans lequel, au démarrage du circuit intégré (CI), on sélectionne en réponse à une commande une action parmi les actions suivantes: - alimenter le module avec la tension d'alimentation (VREG) ayant une valeur fixe sélectionnée parmi une pluralité de valeurs prédéterminées ; - faire varier la valeur de la tension d'alimentation (VREG) au rythme d'un signal impulsionnel (SI).
FR1854118A 2018-05-17 2018-05-17 Procede de gestion de la valeur de la tension d'alimentation d'un module d'un circuit integre, et circuit integre associe Active FR3081241B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1854118A FR3081241B1 (fr) 2018-05-17 2018-05-17 Procede de gestion de la valeur de la tension d'alimentation d'un module d'un circuit integre, et circuit integre associe
US16/411,819 US10949572B2 (en) 2018-05-17 2019-05-14 Method for managing the value of the supply voltage for a module of an integrated circuit, and associated integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1854118 2018-05-17
FR1854118A FR3081241B1 (fr) 2018-05-17 2018-05-17 Procede de gestion de la valeur de la tension d'alimentation d'un module d'un circuit integre, et circuit integre associe

Publications (2)

Publication Number Publication Date
FR3081241A1 FR3081241A1 (fr) 2019-11-22
FR3081241B1 true FR3081241B1 (fr) 2020-05-29

Family

ID=63896245

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1854118A Active FR3081241B1 (fr) 2018-05-17 2018-05-17 Procede de gestion de la valeur de la tension d'alimentation d'un module d'un circuit integre, et circuit integre associe

Country Status (2)

Country Link
US (1) US10949572B2 (fr)
FR (1) FR3081241B1 (fr)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6419159B1 (en) * 1999-06-14 2002-07-16 Microsoft Corporation Integrated circuit device with power analysis protection circuitry
FR2822988B1 (fr) * 2001-04-02 2003-08-15 Oberthur Card Syst Sa Procede de protection d'une entite electronique a microcircuit et entite electronique dotee d'une telle protection
US8912814B2 (en) * 2012-11-12 2014-12-16 Chaologix, Inc. Clocked charge domain logic
US9287772B2 (en) * 2013-03-06 2016-03-15 Vidatronic, Inc. Voltage regulators with improved startup, shutdown, and transient behavior
US10572619B2 (en) * 2016-06-29 2020-02-25 Bar-Ilan University Pseudo-asynchronous digital circuit design
KR102601216B1 (ko) * 2016-09-29 2023-11-10 삼성전자주식회사 반도체 장치의 설계 방법

Also Published As

Publication number Publication date
US20190354728A1 (en) 2019-11-21
FR3081241A1 (fr) 2019-11-22
US10949572B2 (en) 2021-03-16

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