FR3047348B1 - Protection de donnees pour une memoire a autotest integre - Google Patents
Protection de donnees pour une memoire a autotest integre Download PDFInfo
- Publication number
- FR3047348B1 FR3047348B1 FR1650856A FR1650856A FR3047348B1 FR 3047348 B1 FR3047348 B1 FR 3047348B1 FR 1650856 A FR1650856 A FR 1650856A FR 1650856 A FR1650856 A FR 1650856A FR 3047348 B1 FR3047348 B1 FR 3047348B1
- Authority
- FR
- France
- Prior art keywords
- test
- data protection
- memory
- test memory
- integrated self
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/27—Built-in tests
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
- G06F11/0778—Dumping, i.e. gathering error/state information after a fault for later diagnosis
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/36—Data generation devices, e.g. data inverters
- G11C2029/3602—Pattern generator
Abstract
L'invention concerne un procédé comprenant, en réponse à l'activation d'au moins un signal de commande (BIST CMD) requérant qu'un circuit de test (204) d'une matrice mémoire (202) déclenche un mode de test de la mémoire permettant la lecture d'au moins une partie de la matrice mémoire, le lancement par un circuit de commande de test (208) d'une séquence de sur-écriture pour sur-écrire les données stockées dans la matrice mémoire (202) ; et l'activation, grâce au circuit de commande de test (208), du mode de test de la mémoire une fois que la séquence de sur-écriture est achevée.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1650856A FR3047348B1 (fr) | 2016-02-03 | 2016-02-03 | Protection de donnees pour une memoire a autotest integre |
US15/253,002 US10331530B2 (en) | 2016-02-03 | 2016-08-31 | Data protection for memory with built-in self-test |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1650856 | 2016-02-03 | ||
FR1650856A FR3047348B1 (fr) | 2016-02-03 | 2016-02-03 | Protection de donnees pour une memoire a autotest integre |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3047348A1 FR3047348A1 (fr) | 2017-08-04 |
FR3047348B1 true FR3047348B1 (fr) | 2018-07-27 |
Family
ID=56322019
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1650856A Expired - Fee Related FR3047348B1 (fr) | 2016-02-03 | 2016-02-03 | Protection de donnees pour une memoire a autotest integre |
Country Status (2)
Country | Link |
---|---|
US (1) | US10331530B2 (fr) |
FR (1) | FR3047348B1 (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102518881B1 (ko) * | 2017-01-09 | 2023-04-05 | 삼성전자주식회사 | 반도체 장치의 동작 방법 |
US11276648B2 (en) | 2018-07-31 | 2022-03-15 | Nvidia Corporation | Protecting chips from electromagnetic pulse attacks using an antenna |
US11494522B2 (en) * | 2019-11-07 | 2022-11-08 | Micron Technology, Inc. | Semiconductor device with self-lock security and associated methods and systems |
US11030124B2 (en) | 2019-11-07 | 2021-06-08 | Micron Technology, Inc. | Semiconductor device with secure access key and associated methods and systems |
US11182308B2 (en) | 2019-11-07 | 2021-11-23 | Micron Technology, Inc. | Semiconductor device with secure access key and associated methods and systems |
KR20210081093A (ko) * | 2019-12-23 | 2021-07-01 | 주식회사 실리콘웍스 | 메모리 컨트롤러, 및 이의 동작 방법 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1585139A1 (fr) * | 2004-04-08 | 2005-10-12 | STMicroelectronics Pvt. Ltd | Testeur sur puce à vitesse élevée pour tester et caractériser des mémoires de types différents |
FR2881836A1 (fr) * | 2005-02-08 | 2006-08-11 | St Microelectronics Sa | Securisation du mode de test d'un circuit integre |
US20070226795A1 (en) * | 2006-02-09 | 2007-09-27 | Texas Instruments Incorporated | Virtual cores and hardware-supported hypervisor integrated circuits, systems, methods and processes of manufacture |
EP2509075B1 (fr) * | 2006-12-14 | 2019-05-15 | Rambus Inc. | Dispositif mémoire à plusieurs dés |
WO2008150939A1 (fr) * | 2007-05-30 | 2008-12-11 | Summit Design Solutions, Inc. | Procédé et dispositif pour protéger des informations contenues dans un circuit intégré |
US7979616B2 (en) * | 2007-06-22 | 2011-07-12 | International Business Machines Corporation | System and method for providing a configurable command sequence for a memory interface device |
JP2009181600A (ja) * | 2008-01-29 | 2009-08-13 | Renesas Technology Corp | 半導体装置 |
US7872931B2 (en) * | 2008-10-14 | 2011-01-18 | Qimonda North America Corp. | Integrated circuit with control circuit for performing retention test |
US20170357829A1 (en) * | 2016-06-13 | 2017-12-14 | Samsung Electronics Co., Ltd. | Integrated circuit, mobile device having the same, and hacking preventing method thereof |
-
2016
- 2016-02-03 FR FR1650856A patent/FR3047348B1/fr not_active Expired - Fee Related
- 2016-08-31 US US15/253,002 patent/US10331530B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20170220443A1 (en) | 2017-08-03 |
US10331530B2 (en) | 2019-06-25 |
FR3047348A1 (fr) | 2017-08-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
FR3047348B1 (fr) | Protection de donnees pour une memoire a autotest integre | |
US10134455B2 (en) | Efficient calibration of a data eye for memory devices | |
WO2017189579A3 (fr) | Mise en mémoire cache de données | |
ES2625761B1 (es) | Método para la automatización en la calibración dosimétrica, reconstrucción y verificación de tratamientos complejos de radioterapia integrada en un entorno y sistema para la puesta en práctica del mismo | |
EP4236650A3 (fr) | Procédé permettant de lire une mémoire flash tridimensionnelle | |
NO20062455L (no) | Streamerstyringorienteringsinnretningsbestemmelsesapparatur og metode | |
US10304522B2 (en) | Method for low power operation and test using DRAM device | |
TW200739109A (en) | Test method, test system and assist board | |
US20150003171A1 (en) | Semiconductor device, semiconductor system including the same and test method thereof | |
KR102247026B1 (ko) | 반도체 메모리 장치 및 그의 테스트 방법 | |
KR101295655B1 (ko) | 시험 장치 및 시험 방법 | |
KR102538991B1 (ko) | 반도체 테스트 장치 및 반도체 테스트 방법 | |
KR20150086933A (ko) | 반도체 메모리 장치 | |
KR20170005328A (ko) | 반도체 장치 및 반도체 시스템 | |
KR102300890B1 (ko) | 반도체 장치 및 그의 구동 방법 | |
AR118445A1 (es) | Sistema y método para el control automático del tiempo de exposición en un instrumento de imágenes | |
ES2569415A1 (es) | Método de ensayo del estado de materiales | |
EP2942714A3 (fr) | Procede de surveillance, appareil de surveillance et dispositif electronique | |
US20170148528A1 (en) | Semiconductor device and semiconductor system including the same | |
KR102125568B1 (ko) | 반도체 장치 및 그 테스트 방법 | |
CN111370049B (zh) | 一种eMMC芯片测试方法和装置 | |
US9508410B1 (en) | Semiconductor device having a secondary address generating unit for generating address signal in response to address signal from a first address generating unit | |
KR101001143B1 (ko) | 비휘발성 메모리장치 및 이의 동작방법 | |
KR20120080352A (ko) | 반도체 메모리 장치 및 이를 위한 병렬 테스트 검증 회로 | |
US20120266034A1 (en) | Semiconductor memory device and test method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 2 |
|
PLSC | Publication of the preliminary search report |
Effective date: 20170804 |
|
PLFP | Fee payment |
Year of fee payment: 3 |
|
PLFP | Fee payment |
Year of fee payment: 5 |
|
ST | Notification of lapse |
Effective date: 20211005 |