FR2935196B1 - Circuit integre a dimensions reduites - Google Patents

Circuit integre a dimensions reduites

Info

Publication number
FR2935196B1
FR2935196B1 FR0855614A FR0855614A FR2935196B1 FR 2935196 B1 FR2935196 B1 FR 2935196B1 FR 0855614 A FR0855614 A FR 0855614A FR 0855614 A FR0855614 A FR 0855614A FR 2935196 B1 FR2935196 B1 FR 2935196B1
Authority
FR
France
Prior art keywords
face
integrated circuit
reduced dimensions
conductive
conductive material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0855614A
Other languages
English (en)
Other versions
FR2935196A1 (fr
Inventor
Stephan Niel
Jean Michel Mirabel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR0855614A priority Critical patent/FR2935196B1/fr
Priority to US12/538,313 priority patent/US8426973B2/en
Publication of FR2935196A1 publication Critical patent/FR2935196A1/fr
Application granted granted Critical
Publication of FR2935196B1 publication Critical patent/FR2935196B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/60—Peripheral circuit regions
    • H10B20/65—Peripheral circuit regions of memory structures of the ROM only type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un circuit intégré (40) comprenant une couche isolante (18) ayant des première et deuxième faces (19, 20) opposées. Le circuit comprend, dans une première zone, des premières portions conductrices (42) d'un premier matériau conducteur, situées dans la couche isolante, affleurant à la première face (20) et se prolongeant par des premiers vias (41) du premier matériau conducteur, de plus petite section et reliant les premières portions conductrices (42) à la deuxième face (19). Il comprend, en outre, dans une seconde zone, des secondes portions conductrices (25) d'un second matériau conducteur différent du premier matériau conducteur et disposées sur la première face et des deuxièmes vias (23) du premier matériau conducteur, au contact des secondes portions conductrices et s'étendant de la première face à la deuxième face.
FR0855614A 2008-08-19 2008-08-19 Circuit integre a dimensions reduites Expired - Fee Related FR2935196B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0855614A FR2935196B1 (fr) 2008-08-19 2008-08-19 Circuit integre a dimensions reduites
US12/538,313 US8426973B2 (en) 2008-08-19 2009-08-10 Integrated circuit of decreased size

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0855614A FR2935196B1 (fr) 2008-08-19 2008-08-19 Circuit integre a dimensions reduites

Publications (2)

Publication Number Publication Date
FR2935196A1 FR2935196A1 (fr) 2010-02-26
FR2935196B1 true FR2935196B1 (fr) 2011-03-18

Family

ID=40289396

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0855614A Expired - Fee Related FR2935196B1 (fr) 2008-08-19 2008-08-19 Circuit integre a dimensions reduites

Country Status (2)

Country Link
US (1) US8426973B2 (fr)
FR (1) FR2935196B1 (fr)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6731007B1 (en) * 1997-08-29 2004-05-04 Hitachi, Ltd. Semiconductor integrated circuit device with vertically stacked conductor interconnections
JP3697044B2 (ja) * 1997-12-19 2005-09-21 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
US6433428B1 (en) * 1998-05-29 2002-08-13 Kabushiki Kaisha Toshiba Semiconductor device with a dual damascene type via contact structure and method for the manufacture of same
DE69828968D1 (de) * 1998-09-25 2005-03-17 St Microelectronics Srl Verbindungsstruktur in mehreren Ebenen
US6124199A (en) * 1999-04-28 2000-09-26 International Business Machines Corporation Method for simultaneously forming a storage-capacitor electrode and interconnect
US6576546B2 (en) * 1999-12-22 2003-06-10 Texas Instruments Incorporated Method of enhancing adhesion of a conductive barrier layer to an underlying conductive plug and contact for ferroelectric applications
KR100386109B1 (ko) * 2000-11-08 2003-06-02 삼성전자주식회사 2단 메탈콘택구조를 가진 반도체 메모리 장치 및 그제조방법
JP2006165365A (ja) * 2004-12-09 2006-06-22 Renesas Technology Corp 半導体装置および半導体装置の製造方法
JP4113199B2 (ja) * 2005-04-05 2008-07-09 株式会社東芝 半導体装置
KR100722787B1 (ko) * 2005-04-25 2007-05-30 삼성전자주식회사 반도체 장치 및 그 제조 방법

Also Published As

Publication number Publication date
FR2935196A1 (fr) 2010-02-26
US8426973B2 (en) 2013-04-23
US20100044874A1 (en) 2010-02-25

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20150430