FR2921754B1 - Procede de fabrication d'un subtrat semiconducteur localise sur une couche isolante - Google Patents
Procede de fabrication d'un subtrat semiconducteur localise sur une couche isolanteInfo
- Publication number
- FR2921754B1 FR2921754B1 FR0757916A FR0757916A FR2921754B1 FR 2921754 B1 FR2921754 B1 FR 2921754B1 FR 0757916 A FR0757916 A FR 0757916A FR 0757916 A FR0757916 A FR 0757916A FR 2921754 B1 FR2921754 B1 FR 2921754B1
- Authority
- FR
- France
- Prior art keywords
- subtract
- semiconductor
- manufacturing
- insulating layer
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76262—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using selective deposition of single crystal silicon, i.e. SEG techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0757916A FR2921754B1 (fr) | 2007-09-28 | 2007-09-28 | Procede de fabrication d'un subtrat semiconducteur localise sur une couche isolante |
PCT/FR2008/051717 WO2009050379A1 (fr) | 2007-09-28 | 2008-09-26 | Procede de fabrication d'un substrat semiconducteur localise sur une couche isolante |
US12/679,271 US8536027B2 (en) | 2007-09-28 | 2008-09-26 | Method for making a semi-conducting substrate located on an insulation layer |
EP08840579A EP2191501A1 (fr) | 2007-09-28 | 2008-09-26 | Procede de fabrication d'un substrat semiconducteur localise sur une couche isolante |
US13/907,547 US9356094B2 (en) | 2007-09-28 | 2013-05-31 | Method for making a semi-conducting substrate located on an insulation layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0757916A FR2921754B1 (fr) | 2007-09-28 | 2007-09-28 | Procede de fabrication d'un subtrat semiconducteur localise sur une couche isolante |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2921754A1 FR2921754A1 (fr) | 2009-04-03 |
FR2921754B1 true FR2921754B1 (fr) | 2009-11-27 |
Family
ID=39678860
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0757916A Expired - Fee Related FR2921754B1 (fr) | 2007-09-28 | 2007-09-28 | Procede de fabrication d'un subtrat semiconducteur localise sur une couche isolante |
Country Status (4)
Country | Link |
---|---|
US (2) | US8536027B2 (fr) |
EP (1) | EP2191501A1 (fr) |
FR (1) | FR2921754B1 (fr) |
WO (1) | WO2009050379A1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3012256A1 (fr) * | 2013-10-17 | 2015-04-24 | St Microelectronics Tours Sas | Composant de puissance vertical haute tension |
DE102019108754A1 (de) * | 2019-03-06 | 2020-09-10 | Infineon Technologies Ag | Halbleitervorrichtung mit einem porösen bereich, waferverbundstruktur und verfahren zum herstellen einerhalbleitervorrichtung |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040245571A1 (en) * | 2003-02-13 | 2004-12-09 | Zhiyuan Cheng | Semiconductor-on-insulator article and method of making same |
JP2005183845A (ja) * | 2003-12-22 | 2005-07-07 | Canon Inc | 多孔質シリコン領域を有する部材、及び、シリコンを含む部材の製造方法 |
FR2887370B1 (fr) * | 2005-06-17 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un transistor isole a canal contraint |
JP2007235056A (ja) * | 2006-03-03 | 2007-09-13 | Toshiba Corp | 半導体装置およびその製造方法 |
-
2007
- 2007-09-28 FR FR0757916A patent/FR2921754B1/fr not_active Expired - Fee Related
-
2008
- 2008-09-26 EP EP08840579A patent/EP2191501A1/fr not_active Withdrawn
- 2008-09-26 WO PCT/FR2008/051717 patent/WO2009050379A1/fr active Application Filing
- 2008-09-26 US US12/679,271 patent/US8536027B2/en active Active
-
2013
- 2013-05-31 US US13/907,547 patent/US9356094B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
FR2921754A1 (fr) | 2009-04-03 |
US20100289123A1 (en) | 2010-11-18 |
US9356094B2 (en) | 2016-05-31 |
US8536027B2 (en) | 2013-09-17 |
WO2009050379A1 (fr) | 2009-04-23 |
US20130264678A1 (en) | 2013-10-10 |
EP2191501A1 (fr) | 2010-06-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20150529 |