FR2875039A1 - Module ayant une puce contenant un circuit integre - Google Patents
Module ayant une puce contenant un circuit integreInfo
- Publication number
- FR2875039A1 FR2875039A1 FR0508677A FR0508677A FR2875039A1 FR 2875039 A1 FR2875039 A1 FR 2875039A1 FR 0508677 A FR0508677 A FR 0508677A FR 0508677 A FR0508677 A FR 0508677A FR 2875039 A1 FR2875039 A1 FR 2875039A1
- Authority
- FR
- France
- Prior art keywords
- chip
- module
- integrated circuit
- chip containing
- plane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/0772—Physical layout of the record carrier
- G06K19/07728—Physical layout of the record carrier the record carrier comprising means for protection against impact or bending, e.g. protective shells or stress-absorbing layers around the integrated circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Theoretical Computer Science (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Credit Cards Or The Like (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
L'invention concerne un module (1) à puce ayant une puce (2) contenant un circuit intégré. Le module à puce est caractérisé par un élément (8) de renfort qui est relié à la puce et qui a une première partie (4) s'étendant parallèlement au plan de connexion de la puce (2) et au moins une deuxième partie (5) s'étendant en faisant un angle avec ce plan, la puce (2) étant reliée à complémentarité de forme avec la première partie (4) de l'élément (8) de renfort.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004042145A DE102004042145A1 (de) | 2004-08-31 | 2004-08-31 | Chipmodul |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2875039A1 true FR2875039A1 (fr) | 2006-03-10 |
FR2875039B1 FR2875039B1 (fr) | 2009-02-13 |
Family
ID=35745693
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0508677A Expired - Fee Related FR2875039B1 (fr) | 2004-08-31 | 2005-08-23 | Module ayant une puce contenant un circuit integre |
Country Status (4)
Country | Link |
---|---|
US (1) | US20060043575A1 (fr) |
JP (1) | JP2006074044A (fr) |
DE (1) | DE102004042145A1 (fr) |
FR (1) | FR2875039B1 (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102008024823A1 (de) | 2008-05-23 | 2009-12-10 | Smartrac Ip B.V. | Chipkarte mit einer Mehrzahl von Komponenten |
DE102009038802A1 (de) | 2009-08-25 | 2011-03-10 | Mühlbauer Ag | Wert- und Sicherheitsdokument in der Form eines Buches, Verfahren zur Herstellung eines derartigen Wert- und Sicherheitsdokumentes |
CA2771787C (fr) * | 2009-08-26 | 2017-07-04 | Toppan Printing Co., Ltd. | Support de communication sans contact |
DE102010002464A1 (de) * | 2010-03-01 | 2011-09-01 | Bundesdruckerei Gmbh | Dokument mit einem Buchdeckel |
US20180025965A1 (en) * | 2016-07-19 | 2018-01-25 | Dialog Semiconductor (Uk) Limited | WFCQFN (Very-Very Thin Flip Chip Quad Flat No Lead) with Embedded Component on Leadframe and Method Therefor |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04123448A (ja) * | 1990-09-14 | 1992-04-23 | Toshiba Corp | 半導体実装装置 |
JPH08116016A (ja) * | 1994-10-15 | 1996-05-07 | Toshiba Corp | リードフレーム及び半導体装置 |
DE4446566A1 (de) * | 1994-12-24 | 1996-06-27 | Telefunken Microelectron | Mehrpoliges, oberflächenmontierbares, elektronisches Bauelement |
US6166434A (en) * | 1997-09-23 | 2000-12-26 | Lsi Logic Corporation | Die clip assembly for semiconductor package |
JP3719863B2 (ja) * | 1998-12-10 | 2005-11-24 | 三井化学株式会社 | 半導体パッケージおよび製造方法 |
JP3876088B2 (ja) * | 1999-01-29 | 2007-01-31 | ローム株式会社 | 半導体チップおよびマルチチップ型半導体装置 |
JP2001170721A (ja) * | 1999-10-08 | 2001-06-26 | Shinko Electric Ind Co Ltd | 凹部を具備する板状体及びその製造方法ならびに凹部形成用プレス金型 |
DE19962176A1 (de) * | 1999-12-22 | 2001-07-12 | Infineon Technologies Ag | Verfahren zur Herstellung eines Ball-Grid-Array-Gehäuses und Ball-Grid-Array-Gehäuse |
IT1319406B1 (it) * | 2000-04-28 | 2003-10-10 | St Microelectronics Srl | Involucro protettivo per il contenimento di un circuito integrato susemiconduttore. |
TW525274B (en) * | 2001-03-05 | 2003-03-21 | Samsung Electronics Co Ltd | Ultra thin semiconductor package having different thickness of die pad and leads, and method for manufacturing the same |
DE10137619A1 (de) * | 2001-08-01 | 2003-02-27 | Infineon Technologies Ag | Abdeckelement für Baugruppen |
US6573592B2 (en) * | 2001-08-21 | 2003-06-03 | Micron Technology, Inc. | Semiconductor die packages with standard ball grid array footprint and method for assembling the same |
TW563232B (en) * | 2002-08-23 | 2003-11-21 | Via Tech Inc | Chip scale package and method of fabricating the same |
US7161238B2 (en) * | 2002-12-31 | 2007-01-09 | Intel Corporation | Structural reinforcement for electronic substrate |
JP4173751B2 (ja) * | 2003-02-28 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置 |
US20050230842A1 (en) * | 2004-04-20 | 2005-10-20 | Texas Instruments Incorporated | Multi-chip flip package with substrate for inter-die coupling |
US7091581B1 (en) * | 2004-06-14 | 2006-08-15 | Asat Limited | Integrated circuit package and process for fabricating the same |
-
2004
- 2004-08-31 DE DE102004042145A patent/DE102004042145A1/de not_active Withdrawn
-
2005
- 2005-08-23 FR FR0508677A patent/FR2875039B1/fr not_active Expired - Fee Related
- 2005-08-29 JP JP2005248503A patent/JP2006074044A/ja active Pending
- 2005-08-30 US US11/216,457 patent/US20060043575A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
FR2875039B1 (fr) | 2009-02-13 |
DE102004042145A1 (de) | 2006-03-02 |
JP2006074044A (ja) | 2006-03-16 |
US20060043575A1 (en) | 2006-03-02 |
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Legal Events
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Year of fee payment: 12 |
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Year of fee payment: 14 |
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PLFP | Fee payment |
Year of fee payment: 15 |
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PLFP | Fee payment |
Year of fee payment: 16 |
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ST | Notification of lapse |
Effective date: 20220405 |