FR2871920B1 - Circuit de memorisation rapide comprenant une memoire a double acces et procede d'activation d'une memoire a double acces - Google Patents

Circuit de memorisation rapide comprenant une memoire a double acces et procede d'activation d'une memoire a double acces

Info

Publication number
FR2871920B1
FR2871920B1 FR0451190A FR0451190A FR2871920B1 FR 2871920 B1 FR2871920 B1 FR 2871920B1 FR 0451190 A FR0451190 A FR 0451190A FR 0451190 A FR0451190 A FR 0451190A FR 2871920 B1 FR2871920 B1 FR 2871920B1
Authority
FR
France
Prior art keywords
access memory
double access
activation
memory
fast
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0451190A
Other languages
English (en)
Other versions
FR2871920A1 (fr
Inventor
Jean Pierre Schoellkopf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0451190A priority Critical patent/FR2871920B1/fr
Priority to US11/157,133 priority patent/US7307891B2/en
Publication of FR2871920A1 publication Critical patent/FR2871920A1/fr
Application granted granted Critical
Publication of FR2871920B1 publication Critical patent/FR2871920B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
FR0451190A 2004-06-18 2004-06-18 Circuit de memorisation rapide comprenant une memoire a double acces et procede d'activation d'une memoire a double acces Expired - Fee Related FR2871920B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0451190A FR2871920B1 (fr) 2004-06-18 2004-06-18 Circuit de memorisation rapide comprenant une memoire a double acces et procede d'activation d'une memoire a double acces
US11/157,133 US7307891B2 (en) 2004-06-18 2005-06-20 Fast memory circuits and methods

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0451190A FR2871920B1 (fr) 2004-06-18 2004-06-18 Circuit de memorisation rapide comprenant une memoire a double acces et procede d'activation d'une memoire a double acces

Publications (2)

Publication Number Publication Date
FR2871920A1 FR2871920A1 (fr) 2005-12-23
FR2871920B1 true FR2871920B1 (fr) 2007-01-05

Family

ID=34946058

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0451190A Expired - Fee Related FR2871920B1 (fr) 2004-06-18 2004-06-18 Circuit de memorisation rapide comprenant une memoire a double acces et procede d'activation d'une memoire a double acces

Country Status (2)

Country Link
US (1) US7307891B2 (fr)
FR (1) FR2871920B1 (fr)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6078527A (en) * 1997-07-29 2000-06-20 Motorola, Inc. Pipelined dual port integrated circuit memory
US7024518B2 (en) * 1998-02-13 2006-04-04 Intel Corporation Dual-port buffer-to-memory interface
JP3226886B2 (ja) * 1999-01-29 2001-11-05 エヌイーシーマイクロシステム株式会社 半導体記憶装置とその制御方法
US6816955B1 (en) * 2000-09-29 2004-11-09 Cypress Semiconductor Corp. Logic for providing arbitration for synchronous dual-port memory
US6751151B2 (en) * 2001-04-05 2004-06-15 International Business Machines Corporation Ultra high-speed DDP-SRAM cache
KR100416622B1 (ko) * 2002-04-27 2004-02-05 삼성전자주식회사 동기식 반도체 메모리장치의 컬럼 디코더 인에이블 타이밍제어방법 및 장치

Also Published As

Publication number Publication date
US7307891B2 (en) 2007-12-11
FR2871920A1 (fr) 2005-12-23
US20050281091A1 (en) 2005-12-22

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20150227