FR2861895B1 - Procede et dispositif de connexion de puces - Google Patents

Procede et dispositif de connexion de puces

Info

Publication number
FR2861895B1
FR2861895B1 FR0350774A FR0350774A FR2861895B1 FR 2861895 B1 FR2861895 B1 FR 2861895B1 FR 0350774 A FR0350774 A FR 0350774A FR 0350774 A FR0350774 A FR 0350774A FR 2861895 B1 FR2861895 B1 FR 2861895B1
Authority
FR
France
Prior art keywords
face
electrical connection
connection means
connecting chips
active element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0350774A
Other languages
English (en)
Other versions
FR2861895A1 (fr
Inventor
Francois Marion
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR0350774A priority Critical patent/FR2861895B1/fr
Priority to PCT/FR2004/050549 priority patent/WO2005045934A2/fr
Priority to US10/577,142 priority patent/US7569940B2/en
Priority to EP04805792A priority patent/EP1680814A2/fr
Publication of FR2861895A1 publication Critical patent/FR2861895A1/fr
Application granted granted Critical
Publication of FR2861895B1 publication Critical patent/FR2861895B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/01005—Boron [B]
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    • H01L2924/01006—Carbon [C]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
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    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
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    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
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    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Wire Bonding (AREA)
FR0350774A 2003-11-03 2003-11-03 Procede et dispositif de connexion de puces Expired - Fee Related FR2861895B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR0350774A FR2861895B1 (fr) 2003-11-03 2003-11-03 Procede et dispositif de connexion de puces
PCT/FR2004/050549 WO2005045934A2 (fr) 2003-11-03 2004-10-28 Procede et dispositif de connexion de puces
US10/577,142 US7569940B2 (en) 2003-11-03 2004-10-28 Method and device for connecting chips
EP04805792A EP1680814A2 (fr) 2003-11-03 2004-10-28 Procede et dispositif de connexion de puces

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0350774A FR2861895B1 (fr) 2003-11-03 2003-11-03 Procede et dispositif de connexion de puces

Publications (2)

Publication Number Publication Date
FR2861895A1 FR2861895A1 (fr) 2005-05-06
FR2861895B1 true FR2861895B1 (fr) 2006-02-24

Family

ID=34430070

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0350774A Expired - Fee Related FR2861895B1 (fr) 2003-11-03 2003-11-03 Procede et dispositif de connexion de puces

Country Status (4)

Country Link
US (1) US7569940B2 (fr)
EP (1) EP1680814A2 (fr)
FR (1) FR2861895B1 (fr)
WO (1) WO2005045934A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3355081B1 (fr) * 2017-01-27 2019-06-19 Detection Technology Oy Structure de tuile en composé semi-conducteur à conversion directe

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US577391A (en) * 1897-02-16 Nursery-bottle support
JPS6030171A (ja) * 1983-07-28 1985-02-15 Toshiba Corp 混成集積回路装置
US4743868A (en) * 1985-04-03 1988-05-10 Nippondenso Co., Ltd. High frequency filter for electric instruments
US5396104A (en) * 1989-03-28 1995-03-07 Nippon Steel Corporation Resin coated bonding wire, method of manufacturing the same, and semiconductor device
KR910008832A (ko) * 1989-10-20 1991-05-31 다니이 아끼오 면실장형 네트워어크 전자부품
JP2772739B2 (ja) * 1991-06-20 1998-07-09 いわき電子株式会社 リードレスパッケージの外部電極構造及びその製造方法
US5375041A (en) * 1992-12-02 1994-12-20 Intel Corporation Ra-tab array bump tab tape based I.C. package
US5601459A (en) * 1994-09-29 1997-02-11 North American Specialties Corporation Solder bearing lead and method of fabrication
JP3487524B2 (ja) * 1994-12-20 2004-01-19 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US5646446A (en) * 1995-12-22 1997-07-08 Fairchild Space And Defense Corporation Three-dimensional flexible assembly of integrated circuits
US5635718A (en) * 1996-01-16 1997-06-03 Minnesota Mining And Manufacturing Company Multi-module radiation detecting device and fabrication method
JP3462026B2 (ja) * 1997-01-10 2003-11-05 岩手東芝エレクトロニクス株式会社 半導体装置の製造方法
JP3011233B2 (ja) * 1997-05-02 2000-02-21 日本電気株式会社 半導体パッケージ及びその半導体実装構造
JPH1126678A (ja) * 1997-06-30 1999-01-29 Oki Electric Ind Co Ltd 電子部品のリード構造
DE69938582T2 (de) * 1998-09-09 2009-06-04 Seiko Epson Corp. Halbleiterbauelement, seine herstellung, leiterplatte und elektronischer apparat
DE19923467B4 (de) * 1999-05-21 2004-11-11 Infineon Technologies Ag Halbleitermodul mit mehreren Halbleiterchips und leitender Verbindung mittels flexibler Bänder zwischen den Halbleiterchips
US6670700B1 (en) * 1999-08-19 2003-12-30 Seiko Epson Corporation Interconnect substrate and semiconductor device electronic instrument
US6441476B1 (en) * 2000-10-18 2002-08-27 Seiko Epson Corporation Flexible tape carrier with external terminals formed on interposers
US6444921B1 (en) * 2000-02-03 2002-09-03 Fujitsu Limited Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
JP2002026198A (ja) * 2000-07-04 2002-01-25 Nec Corp 半導体装置及びその製造方法
US6940729B2 (en) * 2001-10-26 2005-09-06 Staktek Group L.P. Integrated circuit stacking system and method
KR100442880B1 (ko) * 2002-07-24 2004-08-02 삼성전자주식회사 적층형 반도체 모듈 및 그 제조방법
US6924551B2 (en) * 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package

Also Published As

Publication number Publication date
US20070111567A1 (en) 2007-05-17
FR2861895A1 (fr) 2005-05-06
US7569940B2 (en) 2009-08-04
WO2005045934A3 (fr) 2006-03-02
WO2005045934A2 (fr) 2005-05-19
EP1680814A2 (fr) 2006-07-19

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