FR2819143A1 - Procede de realisation de plots de connexion sur un circuit imprime - Google Patents

Procede de realisation de plots de connexion sur un circuit imprime Download PDF

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Publication number
FR2819143A1
FR2819143A1 FR0017230A FR0017230A FR2819143A1 FR 2819143 A1 FR2819143 A1 FR 2819143A1 FR 0017230 A FR0017230 A FR 0017230A FR 0017230 A FR0017230 A FR 0017230A FR 2819143 A1 FR2819143 A1 FR 2819143A1
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France
Prior art keywords
layer
depositing
resin
copper
chromium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR0017230A
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English (en)
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FR2819143B1 (fr
Inventor
Myriam Oudart
Francois Bernard
Marie Jose Molino
Bruno Reig
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
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Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR0017230A priority Critical patent/FR2819143B1/fr
Priority to PCT/FR2001/004117 priority patent/WO2002054842A1/fr
Priority to US10/204,561 priority patent/US20030013045A1/en
Priority to EP01989644A priority patent/EP1262094A1/fr
Priority to JP2002555597A priority patent/JP2004517500A/ja
Priority to KR1020027011250A priority patent/KR20020089367A/ko
Publication of FR2819143A1 publication Critical patent/FR2819143A1/fr
Application granted granted Critical
Publication of FR2819143B1 publication Critical patent/FR2819143B1/fr
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3473—Plating of solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
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    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

Ce procédé de réalisation prévoit la réalisation d'une couche de chrome (4) permettant de faire en sorte que le matériau du plot de connexion (8) reste dans une zone parfaitement limitée par la couche de chrome (4).Applications : Plots de connexion pour composants électroniques.

Description

<Desc/Clms Page number 1>
PROCEDE DE REALISATION DE PLOTS DE CONNEXION SUR UN
CIRCUIT IMPRIME
L'invention concerne un procédé de réalisation de plots de connexion et notamment de plots de connexion sur un circuit imprimé ou un circuit intégré.
L'invention est applicable notamment dans la réalisation de plots de connexion de très petites dimensions par exemple de diamètre de 200 u voire moins et d'épaisseur 100 microns voire également moins. De plus, ces plots de connexion doivent être de constitution relativement homogène avec peu de défauts et cela sur l'ensemble du circuit.
Par ailleurs, dans les techniques connues la délimitation à la surface du circuit des dimensions d'un plot de connexion est faite couramment par une couche de matériau isolant. Cette couche d'isolant a une épaisseur non négligeable, ce qui fait que la hauteur du plot de connexion est soit relativement importante soit très peu supérieure à l'épaisseur de la couche d'isolant. De plus, la géométrie du plot est de qualité médiocre. L'invention vise à remédier à ces inconvénients.
L'invention concerne donc un procédé de réalisation de plots de connexion sur un circuit comportant au moins une piste conductrice, caractérisé en ce qu'il comporte les étapes suivantes : a) dépôt d'une fine couche de cuivre et d'une couche de chrome sur la surface de l'ensemble du circuit ; b) dépôt d'une couche de résine et enlèvement de cette résine aux endroits des plots à réaliser et également aux endroits où il n'y a pas de piste conductrice ; c) enlèvement de la couche de chrome aux endroits laissés libres par la résine ; d) retrait de la résine ; e) dépôt d'un film photosensible et réalisation dans ce film d'ouvertures aux endroits où l'on désire réaliser des plots de connexion ; f) dépôt d'un matériau de connexion dans lesdites ouvertures ; g) retrait du film photosensible ;
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h) retrait de la couche de cuivre dans les endroits du circuit non recouverts par la couche de chrome ou par le matériau de connexion ; i) chauffage de l'ensemble de façon à atteindre la température de fusion du matériau de connexion.
Les différents objets et caractéristiques de l'invention vont maintenant être décrits en se reportant à la description qui va suivre faite à titre d'exemple et des figures annexées qui représentent : - les figures 1 à à k, un exemple du procédé de réalisation selon l'invention montrant par des vues en coupe du dispositif réalisé, les différentes étapes du procédé ; - les figures 2a et 2b, un dispositif en vue du dessus à différentes étapes du procédé selon l'invention.
On va donc décrire maintenant un procédé de réalisation selon l'invention.
Au cours d'une première étape, sur un substrat 1 portant au moins une piste conductrice ou un plot conducteur 2, on réalise une fine couche de cuivre 3 puis une fine couche de chrome 4 de quelques microns voire quelques dixièmes de microns.
La figure 2a représente à titre d'exemple, une vue du dessus du dispositif de la figure 1 a. On voit donc sur la figure 2a, qu'à titre d'exemple, le substrat 1 porte un conducteur et une partie élargie correspondant à un plot de connexion. Au cours d'une deuxième étape, telle que représentée en figure 1 b, on réalise le dépôt d'une résine photosensible 5.
Au cours d'une troisième étape, représentée en figure 1c, on enlève par tout procédé connu dans la technique, la résine 5 située aux endroits des plots de connexion à réaliser et également là où il n'y a pas de piste conductrice. La figure 2b représente le dispositif à ce stade du procédé. Au cours d'une quatrième étape, tel que cela est représenté en figure 1d, on procède à l'enlèvement du chrome dans les zones non protégées par la résine 5 par tout procédé et notamment par un procédé d'attaque chimique. Au cours d'une cinquième étape, telle que représenté en figure 1 e, on enlève la couche de résine 5.
Au cours d'une sixième étape (figure 1f), on réalise le dépôt d'un film photosensible 6 et dans cette couche de matériau photosensible 6, on
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réalise des ouvertures correspondant à la surface des plots de connexion à réaliser.
Ensuite, au cours d'une septième étape, on réalise dans les ouvertures ainsi obtenues une surcharge en cuivre 7 (5 à 10 um) sur) a fine couche de cuivre 3 (figure 1g).
Puis, au cours d'une huitième étape représentée en la figure 1h, on procède à un dépôt de matériau conducteur tel que de l'étain-plomb (SnPb), ce dépôt permettra de réaliser un plot de connexion 8.
Au cours d'une neuvième étape, on retire le film de photosensible 6 (figure 1 i).
Puis au cours d'une dixième étape, on retire le cuivre à la surface du circuit dans toutes les zones non protégées par la couche de chrome 4 et le matériau conducteur 8 (figure 1j).
Enfin, au cours d'une onzième étape, on procède à un chauffage de l'ensemble de façon à atteindre le point de fusion du mélange d'étainplomb 8 de telle façon que le mélange d'étain-plomb se mette sous la forme d'un plot quasiment sphérique, la surface de ce plot étant nettement délimitée par la couche de chrome 4 située autour du mélange d'étain-plomb.

Claims (3)

REVENDICATIONS
1. Procédé de réalisation de plots de connexion sur un circuit comportant au moins une piste conductrice, caractérisé en ce qu'il comporte les étapes suivantes : a) dépôt d'une fine couche de cuivre (3) et d'une couche de chrome (4) sur la surface de l'ensemble du circuit ; b) dépôt d'une couche de résine (5) et enlèvement de cette résine aux endroits des plots à réaliser et également aux endroits où il n'y a pas de piste conductrice ; c) enlèvement de la couche de chrome aux endroits laissés libres par la résine (5) ; d) enlèvement de la résine (5) ; e) dépôt d'un film photosensible (6) et réalisation dans ce film d'ouvertures aux endroits où l'on désire réaliser des plots de connexion ; f) dépôt d'un matériau de connexion (8) dans lesdites ouvertures ; g) retrait du film photosensible (6) ; h) retrait de la couche de cuivre dans les endroits du circuit non recouverts par la couche de chrome ou par le matériau de connexion (8) ; i) chauffage de l'ensemble de façon à atteindre la température de fusion du matériau de connexion.
2. Procédé selon la revendication 1, caractérisé en ce que le matériau de connexion est de l'étain-plomb.
3. Procédé selon la revendication 1, caractérisé en ce qu'il prévoit entre les étapes (d) et (e), une étape de dépôt d'une couche de cuivre (7) dans les ouvertures réalisées dans le film (6) de l'étape (e).
FR0017230A 2000-12-28 2000-12-28 Procede de realisation de plots de connexion sur un circuit imprime Expired - Fee Related FR2819143B1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR0017230A FR2819143B1 (fr) 2000-12-28 2000-12-28 Procede de realisation de plots de connexion sur un circuit imprime
PCT/FR2001/004117 WO2002054842A1 (fr) 2000-12-28 2001-12-20 Procede de realisation de plots de connexion sur un circuit imprime
US10/204,561 US20030013045A1 (en) 2000-12-28 2001-12-20 Method for producing bond pads on a printed circuit
EP01989644A EP1262094A1 (fr) 2000-12-28 2001-12-20 Procede de realisation de plots de connexion sur un circuit imprime
JP2002555597A JP2004517500A (ja) 2000-12-28 2001-12-20 印刷回路の上に接続バンプを生成する方法
KR1020027011250A KR20020089367A (ko) 2000-12-28 2001-12-20 인쇄회로상에 본드 패드를 형성하는 방법

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US8901736B2 (en) * 2010-05-28 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Strength of micro-bump joints
CN107709505B (zh) * 2015-05-27 2020-04-28 Ａｇｃ株式会社 拒水拒油剂组合物、其制造方法及物品

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Also Published As

Publication number Publication date
KR20020089367A (ko) 2002-11-29
US20030013045A1 (en) 2003-01-16
FR2819143B1 (fr) 2003-03-07
JP2004517500A (ja) 2004-06-10
EP1262094A1 (fr) 2002-12-04
WO2002054842A1 (fr) 2002-07-11

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