EP1350418A1 - Procede de realisation d'interconnexion dans un circuit imprime multicouches - Google Patents
Procede de realisation d'interconnexion dans un circuit imprime multicouchesInfo
- Publication number
- EP1350418A1 EP1350418A1 EP01271795A EP01271795A EP1350418A1 EP 1350418 A1 EP1350418 A1 EP 1350418A1 EP 01271795 A EP01271795 A EP 01271795A EP 01271795 A EP01271795 A EP 01271795A EP 1350418 A1 EP1350418 A1 EP 1350418A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- metal
- components
- hole
- printed circuit
- covered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the present invention relates to a method for making interconnection in a multilayer printed circuit. It applies for example for digital circuits with high integration density or for microwave circuits.
- a first solution consists in drilling metallized holes over the entire thickness of the printed circuit.
- Such a solution has at least two drawbacks.
- This problem is even more sensitive when the circuit includes a large number of layers, since reliability constraints impose increasing the diameter of the holes when their length is increased.
- the space requirement may be a very important parameter to be taken into account, in particular because of the increasingly severe integration constraints.
- a second drawback specific to these metallized holes is their antenna effect, which can in particular be troublesome in the case where the circuit includes microwave functions. This effect can possibly be eliminated by making buried holes, that is to say by pressing a printed circuit on each side of the multilayer circuit to close the holes.
- An optimized solution is to make metallized holes only between the layers to be connected. If we consider the previous example, this amounts to creating a metallized hole only between the third and the fourth layer, or even between a second and a fourth layer for example. For this purpose, it is possible to simply make metallized holes in each of the layers before assembling them to form the multilayer circuit, each layer being in fact a single double printed circuit. face. Thus, still considering the previous example, a metallized hole is made in the third layer. A delicate problem to be solved is then in particular to ensure reliable electrical contact between the metallized hole and the elements to which it is connected, these elements possibly being, for example, another metallized hole, a conductive track or a conductive plane.
- An object of the invention is in particular to allow the production of a multilayer printed circuit as described above with reliable electrical contacts at the outputs of the metallized holes of the internal layers.
- the subject of the invention is a method for producing interconnections in a multilayer printed circuit comprising a stack of elementary printed circuits, the method being carried out according to the following steps:
- the metallic interfaces are covered with a component of a metallic alloy, the metallic interface of a hole being covered with a first component and the metallic interface of the element to be electrically connected to this hole being covered with the second component of the alloy, these two metallic components being brought into contact during the pressure exerted on the stack to form the multilayer printed circuit;
- the components of the alloy are silver and tin, or even indium and tin, which make it possible to obtain a melting temperature of the metallic compound forming the electrical bonds very much higher than their temperatures of fusion.
- Figure 1 therefore shows, in a partial sectional view, a multilayer printed circuit 1.
- This circuit includes a metallized hole 2 opening on either side of this circuit.
- this metallized hole for example electrically connects elements of the third layer C3 to the fourth layer C4.
- conductive tracks or ground planes supported by these layers C3, C4 are for example crossed by this metallic hole.
- a drawback of this type of connection is that the metallized hole 2 occupies a parasitic surface on the other layers, which poses a problem of space.
- the greater the thickness E of the circuit the larger the diameter ⁇ of the hole 2 must be, in particular for reasons of reliability. In other words, the ratio ⁇ / E must not go below a minimum threshold. Typically, this ratio is for example between 5 and 10.
- this metallized hole has an antenna effect which can in particular be harmful when the circuit 1 includes microwave functions or operates in a microwave environment.
- Figure 2 shows an example of a connection which can eliminate the antenna effect in particular.
- a layer 21, 22, that is to say in fact a monolayer circuit closes the holes 2 on either side of a multilayer printed circuit 1 produced as in the case of FIG. 1.
- Such a buried hole circuit does not, however, solve the problem of space. It also does not always eliminate the antenna effect.
- Figure 3 shows a connection mode which reduces the space occupied by the presence of metallized holes.
- the metallized holes 31, 32, 33, 34, 35 only pass through the layers included between the connection points to be provided.
- a hole 31 electrically connecting the third layer C3 to the fourth layer C4 crosses only the space between these two layers.
- a metallized hole 32 electrically connecting the second layer C2 to the fourth layer C4 crosses the space between these two layers, possibly only the third layer C3 loses space due to the passage of the hole.
- FIG. 4 illustrates an electrical connection between a first hole 32 drilled in an elementary printed circuit 41 and a second hole 32 'drilled in the neighboring elementary printed circuit 42, in the case of a printed circuit as illustrated in FIG. 3
- the electrical contact between these two holes must be reliable.
- this electrical contact must withstand the conventional validation tests of printed circuits such as in particular temperature shocks, that is to say for example cycles of rapid temperature variations between -65 ° C and + 150 ° C .
- the electrical contact between the two holes 32, 32 'must withstand high temperatures when these two elements 32, 32' are welded.
- This welding requires in a conventional process temperatures of about 700 ° C to 800 ° C, and is done under high pressure.
- the reliability of the electrical connection does not arise only for the connection of two metallized holes, but also for the connection of a metallized hole with for example a conductive pad.
- the metallized connection holes 2 pass through the conductive areas of the internal layers to be connected. By the very fact that they cross these ranges, this ensures reliable electrical contact.
- FIG. 5 therefore illustrates a possible first step of the method according to the invention.
- metallized holes 31, 32, 32 ' are made in each of the elementary printed circuits 51, 52 forming the multilayer printed circuit.
- the other components of the circuit are also used, such as for example the internal tracks or reception areas 43.
- the metallized holes 31, 32, 32 ′ are produced in a conventional manner in the elementary printed circuits 51, 52. For this purpose, the latter are for example, prior to drilling, covered with a layer of copper.
- connection holes 31, 32, 32 'and equipped with their metallized track or pads are ready for the following steps of the method according to the invention.
- two holes 32, 32 ′ are to be connected together, and a hole 31 is to be connected with a metallized pad 43.
- FIG. 6 shows in a next step two elements to be electrically connected, by way of example these are two metallized holes 32, 32 '. These metallized holes are covered with a metal interface, for example a metal patch 61, 62 placed at their openings which are to be connected. These metal pellets 61, 62 are for example made of copper. The pellets 61, 62 are for example obtained by etching from the copper layer initially placed on their printed circuit.
- Figures 7a, 7b and 7c illustrate the following steps of the method according to the invention, more particularly the welding operation of the elements to be connected.
- the holes are not shown, only the metal interfaces 61, 62 are shown.
- the metal interfaces 61, 62 are each covered with a component of a metal alloy, a metal interface 61 with a first component 71 and the other metal interface 62 being covered with the second component 72 of the alloy, these two metal components 71, 72 will be brought into contact in the subsequent steps 7b, 7c during the pressure exerted on the stack to form the multilayer printed circuit.
- Pressure is therefore exerted on this stack while raising its temperature so as to create a solid-solid diffusion between these components to form a stable intermetallic compound and a solid-solid diffusion of the interfaces. towards the components of the alloy. Ideally, there is diffusion without fusion of the metals to avoid in particular short-circuits.
- FIG. 7a therefore shows the two metal interfaces 61, 62 each covered with one of the components 71, 72 of the alloy, before pressure of the two elementary printed circuits.
- FIG. 7b shows that the two metals making up the alloy are pressed against each other. At this stage, all the layers are pressed against each other.
- the printed circuit is then subjected to a rise in temperature under pressure. This is reflected in particular by the circulation of a heat flow 73 in the direction of the metal layers 71, 72. Under the effect of heat, the latter begin to diffuse.
- the diffusion temperature of the components of the alloy is low, for example of the order of 200 ° C. for example.
- this compound has great thermal stability, which can for example go up to 600 ° C., or even more, while the process according to the invention does not require a high temperature. Indeed, it can for example be implemented at temperatures of 200 ° C., corresponding in fact to the diffusion temperature of the alloy. In fact, the melting point of the compound 74 forming the electrical bond is advantageously very much higher than the diffusion temperatures of the metals 71, 72 of the alloy. The electrical contact produced by this intermetallic compound is therefore very reliable. In particular, it can withstand severe thermal conditions.
- a bonding layer is disposed between each elementary printed circuit to bond these circuits together.
- the bonding takes under the effect of heat.
- This layer is notably pierced at the level of the electrical contacts to be made between layers.
- the alloy is for example a silver-tin alloy (Ag, Sn). That is to say that a metal interface 61 is covered with a layer of tin 71 and that the other metal interface 62 is covered with a layer of silver.
- These layers are only placed at the locations of the electrical contacts to be made. In particular, it must be avoided that alloy residues remain which would not withstand particularly the high temperatures, precisely because of the relatively low melting temperature of the alloy.
- Other types of alloy are possible, it is possible in particular to use an Indium-Tin alloy (In, Sn).
- the metallic interface in copper can be replaced by a metallic interface in gold.
- the parameters to be regulated are in particular the pressure and the assembly temperature.
- the duration of the process of assembling the layers to form a multilayer printed circuit is comparable to that of manufacturing a multilayer circuit according to a conventional process. It may be necessary to optimize the diameter of the metal pellets 61, 62, 71, 72 of the metallized holes in order to ensure good contacting during pressing of the circuit.
- the pretreatment of the layers before assembly is also to be treated with caution.
- the metals with a low melting point which are used, for example silver, tin or indium, have an ability to oxidize rapidly. It may therefore be necessary to use a suitable means making it possible to limit this phenomenon, on pain of running the risk of obtaining a welding defect originating from a wetting defect. It is also important to control the thickness of the metal deposits.
- the method according to the invention makes it possible to obtain a reliable interconnection at the level of the pellets of the metallized holes. It makes it possible in particular to remove the metallized holes completely passing through the multilayer printed circuits. In a conventional circuit, these holes are in fact a limitation on integration, in particular for digital circuits.
- the elementary printed circuits forming the multilayer circuit can be single-sided or double-sided.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0016776 | 2000-12-21 | ||
FR0016776A FR2818870B1 (fr) | 2000-12-21 | 2000-12-21 | Procede de realisation d'interconnexion dans un circuit imprime multicouches |
PCT/FR2001/003929 WO2002051223A1 (fr) | 2000-12-21 | 2001-12-11 | Procede de realisation d'interconnexion dans un circuit imprime multicouches |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1350418A1 true EP1350418A1 (fr) | 2003-10-08 |
Family
ID=8858004
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP01271795A Withdrawn EP1350418A1 (fr) | 2000-12-21 | 2001-12-11 | Procede de realisation d'interconnexion dans un circuit imprime multicouches |
Country Status (5)
Country | Link |
---|---|
US (1) | US20040060173A1 (fr) |
EP (1) | EP1350418A1 (fr) |
CA (1) | CA2432149A1 (fr) |
FR (1) | FR2818870B1 (fr) |
WO (1) | WO2002051223A1 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014198688A1 (fr) | 2013-06-12 | 2014-12-18 | Thales | Circuit imprime a structure multicouche a faibles pertes dielectriques et refroidi |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060042832A1 (en) * | 2004-08-27 | 2006-03-02 | Kiyoshi Sato | Multilayer circuit board and method of producing the same |
FR2984073B1 (fr) * | 2011-12-13 | 2014-09-12 | Thales Sa | Procede de realisation de carte imprimee |
CN113784547A (zh) * | 2020-06-10 | 2021-12-10 | 深南电路股份有限公司 | 一种印制线路板及其压合方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2008588C2 (de) * | 1970-02-24 | 1972-10-12 | Siemens Ag | Verfahren zur herstellung von loetverbindungen |
US4788766A (en) * | 1987-05-20 | 1988-12-06 | Loral Corporation | Method of fabricating a multilayer circuit board assembly |
US5280414A (en) * | 1990-06-11 | 1994-01-18 | International Business Machines Corp. | Au-Sn transient liquid bonding in high performance laminates |
US5276955A (en) * | 1992-04-14 | 1994-01-11 | Supercomputer Systems Limited Partnership | Multilayer interconnect system for an area array interconnection using solid state diffusion |
US5432998A (en) * | 1993-07-27 | 1995-07-18 | International Business Machines, Corporation | Method of solder bonding processor package |
US5456004A (en) * | 1994-01-04 | 1995-10-10 | Dell Usa, L.P. | Anisotropic interconnect methodology for cost effective manufacture of high density printed circuit boards |
US5905736A (en) * | 1996-04-22 | 1999-05-18 | At&T Corp | Method for the billing of transactions over the internet |
-
2000
- 2000-12-21 FR FR0016776A patent/FR2818870B1/fr not_active Expired - Fee Related
-
2001
- 2001-12-11 WO PCT/FR2001/003929 patent/WO2002051223A1/fr not_active Application Discontinuation
- 2001-12-11 CA CA002432149A patent/CA2432149A1/fr not_active Abandoned
- 2001-12-11 EP EP01271795A patent/EP1350418A1/fr not_active Withdrawn
- 2001-12-11 US US10/451,258 patent/US20040060173A1/en not_active Abandoned
Non-Patent Citations (1)
Title |
---|
See references of WO0251223A1 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014198688A1 (fr) | 2013-06-12 | 2014-12-18 | Thales | Circuit imprime a structure multicouche a faibles pertes dielectriques et refroidi |
Also Published As
Publication number | Publication date |
---|---|
CA2432149A1 (fr) | 2002-06-27 |
US20040060173A1 (en) | 2004-04-01 |
FR2818870A1 (fr) | 2002-06-28 |
WO2002051223A8 (fr) | 2002-08-22 |
WO2002051223A1 (fr) | 2002-06-27 |
FR2818870B1 (fr) | 2005-08-26 |
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Legal Events
Date | Code | Title | Description |
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
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17P | Request for examination filed |
Effective date: 20030709 |
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AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
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17Q | First examination report despatched |
Effective date: 20040211 |
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17Q | First examination report despatched |
Effective date: 20040211 |
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GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
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RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: SECHER, SYLVIE,THALES INTELLECTUAL PROPERTY Inventor name: LEDAIN, BERNARD,THALES INTELLECTUAL PROPERTY Inventor name: KERTESZ, PHILIPPE,THALES INTELLECTUAL PROPERTY |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
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18D | Application deemed to be withdrawn |
Effective date: 20080701 |