FR2771510B1 - Cellule de test pour circuit integre et circuit integre l'incorporant - Google Patents
Cellule de test pour circuit integre et circuit integre l'incorporantInfo
- Publication number
- FR2771510B1 FR2771510B1 FR9714647A FR9714647A FR2771510B1 FR 2771510 B1 FR2771510 B1 FR 2771510B1 FR 9714647 A FR9714647 A FR 9714647A FR 9714647 A FR9714647 A FR 9714647A FR 2771510 B1 FR2771510 B1 FR 2771510B1
- Authority
- FR
- France
- Prior art keywords
- integrated circuit
- same
- test cell
- incorporating
- circuit incorporating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9714647A FR2771510B1 (fr) | 1997-11-21 | 1997-11-21 | Cellule de test pour circuit integre et circuit integre l'incorporant |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9714647A FR2771510B1 (fr) | 1997-11-21 | 1997-11-21 | Cellule de test pour circuit integre et circuit integre l'incorporant |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2771510A1 FR2771510A1 (fr) | 1999-05-28 |
FR2771510B1 true FR2771510B1 (fr) | 2000-05-12 |
Family
ID=9513651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9714647A Expired - Fee Related FR2771510B1 (fr) | 1997-11-21 | 1997-11-21 | Cellule de test pour circuit integre et circuit integre l'incorporant |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2771510B1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105593694B (zh) | 2014-08-15 | 2019-02-12 | 华为技术有限公司 | 测试装置和可测试性异步电路 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63182585A (ja) * | 1987-01-26 | 1988-07-27 | Toshiba Corp | テスト容易化機能を備えた論理回路 |
US5005173A (en) * | 1988-12-07 | 1991-04-02 | Texas Instruments Incorporated | Parallel module testing |
DE3923764C1 (fr) * | 1989-07-18 | 1990-08-02 | Siemens Ag, 1000 Berlin Und 8000 Muenchen, De | |
US5533032A (en) * | 1991-10-28 | 1996-07-02 | Sequoia Semiconductor, Inc. | Built-in self-test global clock drive architecture |
US5592493A (en) * | 1994-09-13 | 1997-01-07 | Motorola Inc. | Serial scan chain architecture for a data processing system and method of operation |
JP3652765B2 (ja) * | 1994-12-16 | 2005-05-25 | テキサス インスツルメンツ インコーポレイテツド | 低オーバーヘッドの入力および出力境界走査セル |
-
1997
- 1997-11-21 FR FR9714647A patent/FR2771510B1/fr not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2771510A1 (fr) | 1999-05-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20070731 |