FR2715746B1 - Procédé et système de remise à zéro d'un registre tampon de surveillance latérale de translation. - Google Patents

Procédé et système de remise à zéro d'un registre tampon de surveillance latérale de translation.

Info

Publication number
FR2715746B1
FR2715746B1 FR9500892A FR9500892A FR2715746B1 FR 2715746 B1 FR2715746 B1 FR 2715746B1 FR 9500892 A FR9500892 A FR 9500892A FR 9500892 A FR9500892 A FR 9500892A FR 2715746 B1 FR2715746 B1 FR 2715746B1
Authority
FR
France
Prior art keywords
resetting
lateral movement
buffer register
movement monitoring
monitoring buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9500892A
Other languages
English (en)
Other versions
FR2715746A1 (fr
Inventor
Yamada Yoshihisa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2715746A1 publication Critical patent/FR2715746A1/fr
Application granted granted Critical
Publication of FR2715746B1 publication Critical patent/FR2715746B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/682—Multiprocessor TLB consistency
FR9500892A 1994-01-28 1995-01-26 Procédé et système de remise à zéro d'un registre tampon de surveillance latérale de translation. Expired - Fee Related FR2715746B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6008061A JP2806778B2 (ja) 1994-01-28 1994-01-28 変換索引バッファクリア命令処理方式

Publications (2)

Publication Number Publication Date
FR2715746A1 FR2715746A1 (fr) 1995-08-04
FR2715746B1 true FR2715746B1 (fr) 1998-02-06

Family

ID=11682836

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9500892A Expired - Fee Related FR2715746B1 (fr) 1994-01-28 1995-01-26 Procédé et système de remise à zéro d'un registre tampon de surveillance latérale de translation.

Country Status (3)

Country Link
US (1) US5928353A (fr)
JP (1) JP2806778B2 (fr)
FR (1) FR2715746B1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7234027B2 (en) * 2001-10-24 2007-06-19 Cray Inc. Instructions for test & set with selectively enabled cache invalidate
US7162608B2 (en) * 2001-10-24 2007-01-09 Cray, Inc. Translation lookaside buffer-based memory system and method for use in a computer having a plurality of processor element
US7617378B2 (en) * 2003-04-28 2009-11-10 International Business Machines Corporation Multiprocessor system with retry-less TLBI protocol
US9454490B2 (en) 2003-05-12 2016-09-27 International Business Machines Corporation Invalidating a range of two or more translation table entries and instruction therefore
US7530067B2 (en) * 2003-05-12 2009-05-05 International Business Machines Corporation Filtering processor requests based on identifiers
US7284100B2 (en) * 2003-05-12 2007-10-16 International Business Machines Corporation Invalidating storage, clearing buffer entries, and an instruction therefor
US7281116B2 (en) * 2004-07-30 2007-10-09 Hewlett-Packard Development Company, L.P. Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes
US7631147B2 (en) * 2006-12-06 2009-12-08 Microsoft Corporation Efficient flushing of translation lookaside buffers in a multiprocessor environment
US8051338B2 (en) * 2007-07-19 2011-11-01 Cray Inc. Inter-asic data transport using link control block manager
US9182984B2 (en) 2012-06-15 2015-11-10 International Business Machines Corporation Local clearing control
DK3255550T3 (da) * 2016-06-08 2019-07-15 Google Llc TLB shootdowns til lave omkostninger
US10540292B2 (en) 2016-06-08 2020-01-21 Google Llc TLB shootdowns for low overhead

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4456954A (en) * 1981-06-15 1984-06-26 International Business Machines Corporation Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations
JPS6091462A (ja) * 1983-10-26 1985-05-22 Toshiba Corp 演算制御装置
US4779188A (en) * 1983-12-14 1988-10-18 International Business Machines Corporation Selective guest system purge control
JPS60130995A (ja) * 1983-12-19 1985-07-12 Nippon Telegr & Teleph Corp <Ntt> プロセツサ間通信制御方式
JPS60254346A (ja) * 1984-05-31 1985-12-16 Toshiba Corp マルチプロセツサシステム
JPH01109452A (ja) * 1987-10-22 1989-04-26 Fujitsu Ltd 変換索引バッファ情報の消去制御方式
JPH01234964A (ja) * 1988-03-16 1989-09-20 Fujitsu Ltd マルチプロセッサ制御方式
US5317754A (en) * 1990-10-23 1994-05-31 International Business Machines Corporation Method and apparatus for enabling an interpretive execution subset
US5317705A (en) * 1990-10-24 1994-05-31 International Business Machines Corporation Apparatus and method for TLB purge reduction in a multi-level machine system
US5500948A (en) * 1991-10-29 1996-03-19 Intel Corporation Translating instruction pointer virtual addresses to physical addresses for accessing an instruction cache
JPH05250332A (ja) * 1992-03-05 1993-09-28 Juki Corp 電子機器
US5428757A (en) * 1992-04-29 1995-06-27 International Business Machines Corporation Method for reducing translation look aside buffer purges in a multitasking system

Also Published As

Publication number Publication date
JPH07219915A (ja) 1995-08-18
US5928353A (en) 1999-07-27
FR2715746A1 (fr) 1995-08-04
JP2806778B2 (ja) 1998-09-30

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Legal Events

Date Code Title Description
ST Notification of lapse