FR2688612A1 - Dispositif d'antememoire. - Google Patents

Dispositif d'antememoire. Download PDF

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Publication number
FR2688612A1
FR2688612A1 FR9203054A FR9203054A FR2688612A1 FR 2688612 A1 FR2688612 A1 FR 2688612A1 FR 9203054 A FR9203054 A FR 9203054A FR 9203054 A FR9203054 A FR 9203054A FR 2688612 A1 FR2688612 A1 FR 2688612A1
Authority
FR
France
Prior art keywords
banks
bank
data
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR9203054A
Other languages
English (en)
French (fr)
Other versions
FR2688612B1 (enExample
Inventor
Seznec Andre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institut National de Recherche en Informatique et en Automatique INRIA
Research Centre INRIA Sophia Antipolis - Méditerranée
Original Assignee
Institut National de Recherche en Informatique et en Automatique INRIA
Research Centre INRIA Sophia Antipolis - Méditerranée
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institut National de Recherche en Informatique et en Automatique INRIA, Research Centre INRIA Sophia Antipolis - Méditerranée filed Critical Institut National de Recherche en Informatique et en Automatique INRIA
Priority to FR9203054A priority Critical patent/FR2688612A1/fr
Priority to EP93905448A priority patent/EP0630498B1/fr
Priority to JP5515384A priority patent/JPH08504042A/ja
Priority to US08/302,695 priority patent/US6272592B1/en
Priority to PCT/FR1993/000212 priority patent/WO1993018458A1/fr
Priority to DE69303815T priority patent/DE69303815T2/de
Publication of FR2688612A1 publication Critical patent/FR2688612A1/fr
Application granted granted Critical
Publication of FR2688612B1 publication Critical patent/FR2688612B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G06F12/127—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning using additional replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR9203054A 1992-03-13 1992-03-13 Dispositif d'antememoire. Granted FR2688612A1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR9203054A FR2688612A1 (fr) 1992-03-13 1992-03-13 Dispositif d'antememoire.
EP93905448A EP0630498B1 (fr) 1992-03-13 1993-03-02 Dispositif d'antememoire
JP5515384A JPH08504042A (ja) 1992-03-13 1993-03-02 キャッシュメモリ装置
US08/302,695 US6272592B1 (en) 1992-03-13 1993-03-02 Cache memory device
PCT/FR1993/000212 WO1993018458A1 (fr) 1992-03-13 1993-03-02 Dispositif d'antememoire
DE69303815T DE69303815T2 (de) 1992-03-13 1993-03-02 Cache-speichereinrichtung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9203054A FR2688612A1 (fr) 1992-03-13 1992-03-13 Dispositif d'antememoire.

Publications (2)

Publication Number Publication Date
FR2688612A1 true FR2688612A1 (fr) 1993-09-17
FR2688612B1 FR2688612B1 (enExample) 1997-02-14

Family

ID=9427676

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9203054A Granted FR2688612A1 (fr) 1992-03-13 1992-03-13 Dispositif d'antememoire.

Country Status (6)

Country Link
US (1) US6272592B1 (enExample)
EP (1) EP0630498B1 (enExample)
JP (1) JPH08504042A (enExample)
DE (1) DE69303815T2 (enExample)
FR (1) FR2688612A1 (enExample)
WO (1) WO1993018458A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5659699A (en) 1994-12-09 1997-08-19 International Business Machines Corporation Method and system for managing cache memory utilizing multiple hash functions
US10372358B2 (en) * 2015-11-16 2019-08-06 International Business Machines Corporation Access processor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0080062A2 (en) * 1981-11-23 1983-06-01 International Business Machines Corporation Page controlled cache directory addressing
EP0334479A2 (en) * 1988-03-24 1989-09-27 Nortel Networks Corporation Pseudo set-associative memory cacheing arrangement

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4315312A (en) * 1979-12-19 1982-02-09 Ncr Corporation Cache memory having a variable data block size
US4430712A (en) * 1981-11-27 1984-02-07 Storage Technology Corporation Adaptive domain partitioning of cache memory space
US4894770A (en) * 1987-06-01 1990-01-16 Massachusetts Institute Of Technology Set associative memory
US5133061A (en) * 1987-10-29 1992-07-21 International Business Machines Corporation Mechanism for improving the randomization of cache accesses utilizing abit-matrix multiplication permutation of cache addresses
US5287482A (en) * 1989-01-13 1994-02-15 International Business Machines Corporation Input/output cache
US5434990A (en) * 1990-08-06 1995-07-18 Ncr Corporation Method for serially or concurrently addressing n individually addressable memories each having an address latch and data latch
TW219986B (enExample) * 1991-06-17 1994-02-01 Digital Equipment Corp
US5353424A (en) * 1991-11-19 1994-10-04 Digital Equipment Corporation Fast tag compare and bank select in set associative cache
US5367653A (en) * 1991-12-26 1994-11-22 International Business Machines Corporation Reconfigurable multi-way associative cache memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0080062A2 (en) * 1981-11-23 1983-06-01 International Business Machines Corporation Page controlled cache directory addressing
EP0334479A2 (en) * 1988-03-24 1989-09-27 Nortel Networks Corporation Pseudo set-associative memory cacheing arrangement

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEEE TRANSACTIONS ON COMPUTERS vol. 38, no. 12, Décembre 1989, NEW YORK US pages 1612 - 1630 M. D. HILL ET AL. 'Evaluating associativity in CPU caches' *
PROCEEDINGS OF THE IEEE 1990 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 13 - 16 Mai 1990, Boston, US, pages 2421 - 2424, IEEE, New York, US; E.REESE et al.: 'A sub-10ns cache SRAM, for high performance 32 bit microprocessors' *

Also Published As

Publication number Publication date
US6272592B1 (en) 2001-08-07
EP0630498B1 (fr) 1996-07-24
DE69303815D1 (de) 1996-08-29
FR2688612B1 (enExample) 1997-02-14
JPH08504042A (ja) 1996-04-30
WO1993018458A1 (fr) 1993-09-16
EP0630498A1 (fr) 1994-12-28
DE69303815T2 (de) 1997-03-13

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Effective date: 20071130