FR2604517A1 - ARRANGEMENT FOR DETERMINING AN AVERAGE VALUE - Google Patents

Abstract

THE MEASURED VALUES 19 PROVIDED BY THE MEASURING EQUIPMENT 14 ARE PERIODICALLY TRANSFERRED INTO TOTALIZING MEMORIES 21 MOUNTED UPSTREAM OF THE OUTPUT DIVIDER 25, WHOSE CONTENTS ARE, IN THE EVENT OF EXCEEDING THE CAPACITY OF ONE OF THE MEMORIES 21, REDUCED ACCORDING TO THE IDENTICAL DIVIDERS (AND INCREASED FOR EACH EXCEEDING OF MEMORY CAPACITY). WHERE, IN THIS CASE, THE PREVIOUS BEHAVIOR OF THE MEASURED VALUES 19 IN THE AVERAGE RESULT VALUE 26 MUST KEEP THE SAME WEIGHTING AS THE MEASURED VALUES APPEARING SUBSEQUENTLY AFTER EACH RESET OF THE MEASURING DEVICES 14 IN THEIR INITIAL POSITION, THESE ULTIMATE MEASURED VALUES 19 THEN ALSO DIVIDED BY THE SAME FACTOR AS THE CONTENT ACCUMULATES TOTALIZING MEMORIES 21. NO ROUNDING ERRORS OCCUR, IF ONLY THE ENTIRE FRACTION OF THE DIVISION RESULT IS TRANSMITTED TO THE CORRESPONDING 21 TOTALIZING MEMORY, BUT THE REMAINDER OF MEASUREMENT VALUE 37 OF EACH DIVISION IS RETURNED TO THE CORRESPONDING MEASURING APPARATUS 14 AS THE INITIAL MEASUREMENT POSITION.

Description

ARRANGEMENT FOR DETERMINING AN AVERAGE VALUE

  The present invention relates to an arrangement for determining the mean value of a dependent variable variable quantity (12.1), by means of an independent variable variable quantity (12.2), which detects each of them by means of an integrating measuring device (14.1 , respectively 14.2) and forms the

quotient in a divisor (25).

  We always need such arrangements in measurement technique, when we are interested in the mean value as a quotient of a dependent variable and an independent variable, such as for example the wear of production tooling in function of the output of a manufacturing facility, or an average speed as a quotient of the distance traveled and the time elapsed. When, in such cases, a third related quantity must be determined from two measured quantities by forming their quotient, the highest possible measurement sensitivity must be sought, in order to be able to obtain, already with low values of the independent variables, sufficient precision, therefore usable average value results. On the other hand, beyond the larger independent variable, the dependent variable accumulates to a measured value so large that analog processing arrangements

  can leave the area of non-characteristics

  linear to pass to saturation, while digital information processing results in numerical values so high that they can often no longer be judiciously manipulated with simple technical circuits, due to the fact that, for example, calculation operations take too long. This is particularly the case when, over the total lifetime of a machine (for example, of a motor vehicle>, one has to observe or display

  the average wear of the operating parts.

  In view of these data, the object of the invention is to produce an arrangement of the type indicated, which already provides, over very short intervals of variation of the independent variables, a result of average value of good precision, and which, despite the high measurement resolution necessary for this, does not cause, even after long intervals of the independent variables, loss of information due to saturation phenomena; therefore which makes it possible to detect, over extremely wide intervals independent variables for variations of a variable, only weak influences on the

quotient in the mean value.

  To achieve this objective, according to the invention, there is mounted downstream of each measuring device a totalizing memory which must periodically receive the measured value with the measuring device returning to an initial position, and to each of the totalizing memories there corresponds a stage reducer which reduces the totalized measurement result by a factor, in the event of the capacity of one of the memories being exceeded with rewriting of the reduced measurement value in the corresponding totalizing memory instead of the previous measurement result, which caused the excess capacity, the reduction factor in the reduction stages being increased each time it is exceeded

of memory capacity.

  The solution therefore presents, in a way, a reduced sensitivity to the formation of the quotient almost continuously with the incremental increase in the independent variables. The average value presented in the form of a quotient does not however see its precision reduced when, in the case where one of the variables increases beyond a limit value determined by the technique of the circuits, the accumulated dividend and the divisor accumulated for the formation of the quotient both decrease by a common factor, which is then applied later also as a divisor to the extraction of the measured value. The division of the effective measured value by this - factor is not essential, either, in a numerical realization of the circuits, since it suffices to take account of the whole fraction of the quotient of the measured values and that one can avoid rounding errors by reinserting the fraction remaining after division into the meter; by not losing it when

extracting the measured value.

  In the case of a digital realization of the circuits, the division of the actual measured values is effected, as appropriate, by a divider circuit to which the divider is transmitted from a counter, so that no rounding error can occur. may distort the actual measured value. On the other hand, the accumulated variables coded in binary form can be appropriately reduced simply by shifting the content of shift registers, since the divider for the reduction of the actual and accumulated measured values can be freely chosen. When the exact determination of the average value interests less than the influence of the recent evolution of the measured values compared to the previous evolution, it is enough to increase the divisor for the effective measured value less strongly than the divisor for the variables accumulated. When the divider for the actual measured value is no longer driven, the arrangement according to the invention can be used practically over an unlimited variation interval of the independent variables, since there can be no overflow of register capacity when the division of the accumulated variables takes place by shifting of register register locations

  information encoded in binary form.

  Other variants, developments, characteristics and advantages of the invention

  will emerge from the detailed description which follows

  of two preferred embodiments, represented according to the circuit technique in the appended drawing, very schematic and reduced to the essentials, of which: FIG. 1 represents an arrangement for determining the average value in analog signal processing technique, and FIG. 2 shows a corresponding arrangement, in digital signal processing technique. The block representation of FIG. 1 represents signal processing channels 11.1 and 11.2, respectively for a dependent measured quantity and an independent measured quantity 12.1, 12.2, in the sense of the examples of the aforementioned variables,

  which are detected by means of detectors 13.1, 13.2.

  The integrating measuring devices 14.1 and 14.2, mounted downstream of the detectors 13 are each shown diagrammatically in the form of an operational amplifier 15 with capacitive feedback 16 following the input resistance 17. For reasons of clarity Figures not shown in the drawing of the sampling retaining members for receiving or transferring information with side decoupling

  inlet and outlet side respectively.

  If the initialization is carried out via a control circuit 18, after a certain measurement time interval, the actual measured value 19.1 or 19.2 is called up at the output of the measuring device 14.1 or 14.2, by being transferred, via a switch 20.1 or 20.2, to a totalizing memory 21.1 or 21.2, which can, in principle, have the same structure as the measuring devices 14. It is therefore possible , then erase the measured values 19 by returning the measuring devices 14 to their initial measurement position, which has been represented symbolically in the drawing by a discharge switch 22 for the capacitive feedback 16 of the amplifier 15. When this return of the measuring device 14 to the operating position occurs often enough, it is certain that the amplifier 15 cannot pass to saturation, therefore that the measuring device 14 cannot be saturated with the quantity measured 12. For a behavior d e the measured quantity 12 with strong fluctuation or unknown, it is possible to provide (as shown in dashes on the figure-1) to mount an indicator downstream of the respective output of each of the measuring devices 14.1 and 14.2 of limit value, 23.1 or 23.2, these activating, via an OR circuit 24, the control circuit 18 for the reception of the measured values and the return of the measuring devices 14 in the initial operating position , when, in one of the channels 11, the measured value 19 threatens to reach the limit

saturation.

  There is inserted, downstream of the totalizing memories 21.1 and 21.2, a divider arrangement 25 which supplies, in the form of a quotient, the effective mean value 26 of the measurement result 27.1 totaled for the dependent variable, on the totalized measurement result 27.2 independent variables. This delivery is only almost continuous, insofar as the measurement results 27 actually applied to the divider 25 represent only the total after the last reception of measured value, therefore do not yet take into account the measured value 19 newly accumulated in addition on the measuring device 14. The degree of this discontinuity can be adjusted by means of the control circuit 18, therefore by means of the frequency of repetition of the transfer of the actual measured values 19 in the

totalizing memories 21.

  In addition, the capacity of the totalizing memories 21 is not unlimited. Correspondingly to the measuring devices 14, they are therefore also brought back to their initial position, when the limit value indicators 28.1 or 28.2 react, after the actual measurement result totaled in each case 27.1 or 27.2 has been transferred via a switch, 29.1 or 29.2, in the corresponding reduction stage, 30.1 or 30.2. In these, each measurement result 27 is reduced to a fraction of the actual value, and each memory 21 is set to this reduced measured value 31.1, or 31.2, as measurement result 27.1 / 27.2 to be further processed using of the divider 25. This reduction process is represented, according to the block diagram in FIG. 1, for the reduction stage 30, by an operational amplifier 15 with ohmic (proportional) wiring 32 which is reduced each time by one step additional, when one of the indicators of via an OR 33 input, the mounting of

  command 34 to reduce the measurement result.

  So that, despite this reduction in the totalized measurement result 27, the relationship with the input quantity of the memory 21, therefore with the measured value 19, is still exact, a reduction stage 35.1 or 35.2 is mounted downstream of each measuring device 14.1, 14.2. Since the same reduction in measured value is carried out in each of the two channels 11.1 and 11.2, this has no effect on the average value 26

determined by the divider 25.

  In principle, it is possible to transfer only part of each measured value 19, via the reduction stage 35, to the corresponding totalizing memory 21, as indicated in FIG. 1 by the stages dash dividers 36.1, 36.2. The surplus 37.1, or 37.2 is returned to the corresponding measuring device 14.1 or 14.2 and is taken into account during the next transfer of measured values, so it is not lost when determining the average value 26 This has the advantage of not requiring operation of the measuring devices 14 from zero, and therefore making it possible to avoid areas

  non-linear characteristic.

  According to FIG. 2, the implementation of the solution of the invention from the point of view of the circuit technique is simplified when it is carried out in digital technique. Because the arrangements of FIGS. 1 and 2 correspond to one another as regards the determination of the mean values, the same reference numerals are chosen, as far as possible, from

  so their detailed description is not

required in Figure 2.

  The detectors 13 supply, as measured quantities 12, pulses which are added (counted) in the measuring devices 14, produced in the form of binary counters with several positions. The reduction stages 30 are shift registers, therefore memories for binary digits which can be multiplied or divided by the value TWO simply by shifting the memory contents towards the position of greatest weight or of least weight (therefore "toward the left "or" to the right "in the

classical logical representation).

  In the interest of defined initial states coded in binary form, the control circuit 18 puts, at the start of operation, the measuring devices 14 in the initial counting position ZERO by means of their reset inputs 38 and the shift register of a divider transmitter 45 for the reduction stage 35 to the value UN; while the control circuit 18 sets the shift registers of the reduction stages 30, by means of their setting inputs to a 39, in the reduction stage of dividends 30.1, to the initial value ZERO and, in the stage divider reducer 30.2, at the initial value UN, therefore produced at the output of the divider assembly 25, the

initial mean value 26 ZERO.

  During the transfer of the measured values 19 to the totalizing memories 21, there occurs, in the reduction stages 35, a digital division by the number actually supplied by the data output of the

2 604517

  shift register transmitter 45, as a divider. A modulo stage 41 (which corresponds functionally in this measure to the dividing stages 36 of FIG. 1) certainly does not provide the result of the division, but only the whole part of the quotient, to the totalizing memory 21 (represented in the drawing under the in the form of a digital adder assembly), while the remainder of the division is returned, in the form of a measured value remainder 37, to the data input of the counter measuring device 14, as the counting position initial now (so that it does not enter into the balance of each rounding error memory 21 originating from the digital division, since the rest of the division is again taken into account during the transfer valuable

measured next).

  If overflow information appears on one of the digital totalizing memories 21 (adders) at the transfer output 42, the control assembly 34 is attacked via its OR input 33, to deliver, for Following the processing of the measured values supplied 19, the reduction information 43. In the case of the shift stages of the reduction stages 30 being shift registers, this involves attacking their offset inputs 4, so that the contents of the shift registers are shifted by one position (deletion of the least significant digit), which corresponds to a halving of the contents of the register. At the same time, the content of the registers of the divider transmitter 45 for the reduction stages 35 is shifted by one position, in the sense that the least significant digits arrive in the positions of the neighboring most significant digits, which corresponds to a multiplication by the same constant as in the case of the other shift registers, therefore at a

  doubling of the divider for the reduction stages 35.

  To suppress the overflow in the totalizing memories 21, there is therefore a transcription of the content of the totalizing memory 21 with the reduced value 31, each time there is an overflow and, subsequently, no more is taken taking into account the measured values 19 that reduced. When the capacity of the divider transmitter with the overflow of the shift registers is exhausted, the regular operating limit is reached. Beyond this limit, however, operation can continue with an approximation method for determining the average, the maximum content of the shift registers now remaining retained (under the control of a transfer output 46 on the transmitter divider 45 and a logic element 45>, although the shift registers of the reduction stages 30 continue to progress in a rhythmic fashion with each carryover order

  under the action of one of the totalizing memories 21.

  Because there is therefore no longer a corresponding reduction in the measurement values 19, but that these are subsequently added without reduction, despite the reduction in the summation result in the memory 21, the quotient resulting from the average value 26 is only an approximate result in which the recent development of the measured values 19 takes place more strongly than the old one and is gaining more and more weight. It is, of course, the same for similar measures taken in the case of the

  realization in analog technique of figure 1.

  It is only for reasons of clarity that three individual dividing circuits have been shown in FIG. 2 as reducing stages 35 and output divider 25. Because measured values 19 are only transferred at discrete times, one can also provide, under the control of circuits 18 or 34, a single divider assembly which is inserted cyclically successively downstream of the totalizing memories 21.1 and 21.2 which have just been newly supplied, in order to deliver discontinuous average values 26. In in addition, the digital production of the circuits of FIG. 2 can likewise, in the context of the present invention, be implemented by discrete wiring of components separate from the technique of digital circuits, as well as in the context of a processing of measured values controlled by memory programming

or by means of a microprocessor.

2 6 0 4517

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Claims (7)

  1. Arrangement for determining the average value of a dependent variable variable quantity (12.1) by means of an independent variable variable quantity (12.2), which detects each of them by means of an integrating measuring device (14.1 or 14.2) and form the quotient in a divider (25), characterized in that one ascends downstream of each measuring device (14.1, 14.2) a totalizing memory (21.1, 21.2) which must periodically receive the measured value (19.1 or 19.2) with return of the measuring device (14,1, 14.2) to an initial position, and in that to each of the totalizing memories (21.1 and 21.2) corresponds a reducing stage (30.1 or 30.2) which reduces by a factor the totalized measurement result (27.1 or 27.2>, if one of the memories exceeds the capacity with rewriting of the reduced value measured by the device (31.1 or 31.2) in the corresponding totalizing memory (21.1 or 21.2) instead of the previous measurement result (27.1 or 27.2) which resulted in the overflow, the reduction factor in the reduction stages (30.1 and 30.2) being increased to each overflow.   2. Arrangement according to claim 1, characterized in that provision is made for the measured values (19.1 and 19.2), before each corresponding totalizing memory (21.1 or 21.2>, one stage reducer (35.1 or 35.2).   3 Arrangement according to claim 2, characterized in that the reduction stages (35.1, 35.2) for the measured values (19.1, 19.2) operate with the same respective divider increased in the event of overflow of memory capacity as the reduction stages (30.1, 30.2) for the results of summed measurement (27.1, 27.2).   4. Arrangement according to one of claims   previous characterized in that each time the measuring device (14.1 and 14.2) is reset, only part of the measured value (19.1 or 19.2) is transferred to the totalizing memory (21.1, 21. 2 ) and the rest of the measured value is returned as the initial value to the corresponding measuring device (14.1, or 14.2).   5. Arrangement according to one of claims   previous, characterized by incremental counters that can be positioned as measuring devices (12.1 and 12.2), digital addition circuits as totalizing memories (21.1 and 21.2) for the measured values (19.1 and 19.2) and shift registers that can be shifted step by step as reduction stages (30.1, 30.2) mounted downstream of the totalizing memories (21.1 or 21.2). for totalized binary coded measurement results (27.1 or 27.2) with start command from the carry output (42) of one memories (21.1 or 21.2).   6. Layout according to the whole   claim 5 and one of claims 2 to 4,   characterized by a digital divider circuit, as a reduction stage (35. 1 or 35.2) for the measured values (19.1 and 19.2) with a shift register which can progress under the action of a carry-over output (42) of the memories ( 21.1, 21.2), as a divider transmitter (45), and with a modulo stage (41.1 or 41.2) for transferring the entire result of the division to the subsequent totalizing memory (21.1 or 21.2) and the rest of the measured value of the division (37.1 or 37.2) as the new initial count position at   the corresponding measuring device (14.1 or 14.2).   7. Arrangement according to claim 6, characterized in that there is a single divider circuit comam reduction stage (35.1 or 35.2) and as a divider (25) for the totalized measurement results (27.1 and 27.2), which receives successively, in multiplexed operation, the measured values (19.1 and 19.2), as well as their common divider (40) and the   totalized measurement results (27.1, as well as 27.2).