FR2487125B1 - - Google Patents

Info

Publication number
FR2487125B1
FR2487125B1 FR8114109A FR8114109A FR2487125B1 FR 2487125 B1 FR2487125 B1 FR 2487125B1 FR 8114109 A FR8114109 A FR 8114109A FR 8114109 A FR8114109 A FR 8114109A FR 2487125 B1 FR2487125 B1 FR 2487125B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8114109A
Other versions
FR2487125A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EMC Corp
Original Assignee
Data General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Data General Corp filed Critical Data General Corp
Publication of FR2487125A1 publication Critical patent/FR2487125A1/fr
Application granted granted Critical
Publication of FR2487125B1 publication Critical patent/FR2487125B1/fr
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/947Subphotolithographic processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Weting (AREA)
FR8114109A 1980-07-21 1981-07-20 Procede de formation de zones etroites dans des circuits integres, notamment pour la formation de grilles, l'isolement de composants, la formation de regions dopees et la fabrication de transistors Granted FR2487125A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/170,833 US4318759A (en) 1980-07-21 1980-07-21 Retro-etch process for integrated circuits

Publications (2)

Publication Number Publication Date
FR2487125A1 FR2487125A1 (fr) 1982-01-22
FR2487125B1 true FR2487125B1 (fr) 1984-04-20

Family

ID=22621451

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8114109A Granted FR2487125A1 (fr) 1980-07-21 1981-07-20 Procede de formation de zones etroites dans des circuits integres, notamment pour la formation de grilles, l'isolement de composants, la formation de regions dopees et la fabrication de transistors

Country Status (6)

Country Link
US (1) US4318759A (fr)
JP (1) JPS5787136A (fr)
DE (1) DE3128629A1 (fr)
FR (1) FR2487125A1 (fr)
GB (1) GB2081187B (fr)
IT (1) IT1138064B (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4546066A (en) * 1983-09-27 1985-10-08 International Business Machines Corporation Method for forming narrow images on semiconductor substrates
US4631113A (en) * 1985-12-23 1986-12-23 Signetics Corporation Method for manufacturing a narrow line of photosensitive material
US4906585A (en) * 1987-08-04 1990-03-06 Siemens Aktiengesellschaft Method for manufacturing wells for CMOS transistor circuits separated by insulating trenches
DE3817326A1 (de) * 1988-05-20 1989-11-30 Siemens Ag Verfahren zur herstellung von gitterstrukturen mit um eine halbe gitterperiode gegeneinander versetzten abschnitten
DE3915650A1 (de) * 1989-05-12 1990-11-15 Siemens Ag Verfahren zur strukturierung einer auf einem halbleiterschichtaufbau angeordneten schicht
EP0518418A1 (fr) * 1991-06-10 1992-12-16 Koninklijke Philips Electronics N.V. Procédé de fabrication d'un dispositif semiconducteur consistant à former par oxydation des régions d'oxyde de champ dans une surface d'un corps semiconducteur
DE10052955A1 (de) * 2000-10-25 2002-06-06 Tesa Ag Verwendung von Haftklebemassen mit anisotropen Eigenschaften für Stanzprodukte
ITMI20042243A1 (it) 2004-11-19 2005-02-19 St Microelectronics Srl Processo per la realizzazione di un dispositivo mos di potenza ad alta densita' di integrazione
US7875936B2 (en) * 2004-11-19 2011-01-25 Stmicroelectronics, S.R.L. Power MOS electronic device and corresponding realizing method
FR2880471B1 (fr) * 2004-12-31 2007-03-09 Altis Semiconductor Snc Procede de nettoyage d'un semiconducteur

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1559608A (fr) * 1967-06-30 1969-03-14
NL157662B (nl) * 1969-05-22 1978-08-15 Philips Nv Werkwijze voor het etsen van een oppervlak onder toepassing van een etsmasker, alsmede voorwerpen, verkregen door toepassing van deze werkwijze.
US3764865A (en) * 1970-03-17 1973-10-09 Rca Corp Semiconductor devices having closely spaced contacts
DE2139631C3 (de) * 1971-08-07 1979-05-10 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zum Herstellen eines Halbleiterbauelements, bei dem der Rand einer Diffusionszone auf den Rand einer polykristallinen Siliciumelektrode ausgerichtet ist
US4124933A (en) * 1974-05-21 1978-11-14 U.S. Philips Corporation Methods of manufacturing semiconductor devices
JPS5131186A (fr) * 1974-09-11 1976-03-17 Hitachi Ltd
US4063992A (en) * 1975-05-27 1977-12-20 Fairchild Camera And Instrument Corporation Edge etch method for producing narrow openings to the surface of materials
GB1543845A (en) * 1975-05-27 1979-04-11 Fairchild Camera Instr Co Production of a narrow opening to a surface of a material
US3966514A (en) * 1975-06-30 1976-06-29 Ibm Corporation Method for forming dielectric isolation combining dielectric deposition and thermal oxidation
US4040168A (en) * 1975-11-24 1977-08-09 Rca Corporation Fabrication method for a dual gate field-effect transistor
US4053349A (en) * 1976-02-02 1977-10-11 Intel Corporation Method for forming a narrow gap
US4239559A (en) * 1978-04-21 1980-12-16 Hitachi, Ltd. Method for fabricating a semiconductor device by controlled diffusion between adjacent layers
DE2902665A1 (de) * 1979-01-24 1980-08-07 Siemens Ag Verfahren zum herstellen von integrierten mos-schaltungen in silizium-gate- technologie

Also Published As

Publication number Publication date
US4318759A (en) 1982-03-09
IT1138064B (it) 1986-09-10
JPS5787136A (en) 1982-05-31
IT8122944A0 (it) 1981-07-15
DE3128629A1 (de) 1982-06-09
GB2081187A (en) 1982-02-17
FR2487125A1 (fr) 1982-01-22
GB2081187B (en) 1984-03-07

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Legal Events

Date Code Title Description
ST Notification of lapse