FR2472268A1 - Procede de formation de caisson dans des circuits integres - Google Patents

Procede de formation de caisson dans des circuits integres Download PDF

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Publication number
FR2472268A1
FR2472268A1 FR7931483A FR7931483A FR2472268A1 FR 2472268 A1 FR2472268 A1 FR 2472268A1 FR 7931483 A FR7931483 A FR 7931483A FR 7931483 A FR7931483 A FR 7931483A FR 2472268 A1 FR2472268 A1 FR 2472268A1
Authority
FR
France
Prior art keywords
type
conductivity
walls
substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7931483A
Other languages
English (en)
French (fr)
Other versions
FR2472268B1 (OSRAM
Inventor
Eugene Tonnel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR7931483A priority Critical patent/FR2472268A1/fr
Priority to DE8080401616T priority patent/DE3065715D1/de
Priority to EP80401616A priority patent/EP0031260B1/fr
Priority to US06/212,974 priority patent/US4369561A/en
Publication of FR2472268A1 publication Critical patent/FR2472268A1/fr
Application granted granted Critical
Publication of FR2472268B1 publication Critical patent/FR2472268B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H10P90/191—
    • H10P50/00—
    • H10W10/031—
    • H10W10/181—
    • H10W10/30—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion

Landscapes

  • Element Separation (AREA)
FR7931483A 1979-12-21 1979-12-21 Procede de formation de caisson dans des circuits integres Granted FR2472268A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR7931483A FR2472268A1 (fr) 1979-12-21 1979-12-21 Procede de formation de caisson dans des circuits integres
DE8080401616T DE3065715D1 (en) 1979-12-21 1980-11-12 Process for aligning photogravures with respect to region-isolating walls in integrated circuits
EP80401616A EP0031260B1 (fr) 1979-12-21 1980-11-12 Procédé d'alignement de photogravures par rapport aux murs d'isolement de caisson dans des circuits intégrés
US06/212,974 US4369561A (en) 1979-12-21 1980-12-04 Process for aligning diffusion masks with respect to isolating walls of coffers in integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7931483A FR2472268A1 (fr) 1979-12-21 1979-12-21 Procede de formation de caisson dans des circuits integres

Publications (2)

Publication Number Publication Date
FR2472268A1 true FR2472268A1 (fr) 1981-06-26
FR2472268B1 FR2472268B1 (OSRAM) 1983-10-14

Family

ID=9233091

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7931483A Granted FR2472268A1 (fr) 1979-12-21 1979-12-21 Procede de formation de caisson dans des circuits integres

Country Status (4)

Country Link
US (1) US4369561A (OSRAM)
EP (1) EP0031260B1 (OSRAM)
DE (1) DE3065715D1 (OSRAM)
FR (1) FR2472268A1 (OSRAM)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532700A (en) * 1984-04-27 1985-08-06 International Business Machines Corporation Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer
US4627883A (en) * 1985-04-01 1986-12-09 Gte Laboratories Incorporated Method of forming an isolated semiconductor structure
JPH01179342A (ja) * 1988-01-05 1989-07-17 Toshiba Corp 複合半導体結晶体

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3954523A (en) * 1975-04-14 1976-05-04 International Business Machines Corporation Process for fabricating devices having dielectric isolation utilizing anodic treatment and selective oxidation
DE2633134A1 (de) * 1975-07-26 1977-02-10 Int Computers Ltd Integrierte schaltanordnung
US4016017A (en) * 1975-11-28 1977-04-05 International Business Machines Corporation Integrated circuit isolation structure and method for producing the isolation structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3713908A (en) * 1970-05-15 1973-01-30 Ibm Method of fabricating lateral transistors and complementary transistors
DE2044863A1 (de) * 1970-09-10 1972-03-23 Siemens Ag Verfahren zur Herstellung von Schottkydioden
GB1501114A (en) * 1974-04-25 1978-02-15 Rca Corp Method of making a semiconductor device
US3919060A (en) * 1974-06-14 1975-11-11 Ibm Method of fabricating semiconductor device embodying dielectric isolation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3954523A (en) * 1975-04-14 1976-05-04 International Business Machines Corporation Process for fabricating devices having dielectric isolation utilizing anodic treatment and selective oxidation
DE2633134A1 (de) * 1975-07-26 1977-02-10 Int Computers Ltd Integrierte schaltanordnung
US4016017A (en) * 1975-11-28 1977-04-05 International Business Machines Corporation Integrated circuit isolation structure and method for producing the isolation structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/77 *

Also Published As

Publication number Publication date
DE3065715D1 (en) 1983-12-29
EP0031260B1 (fr) 1983-11-23
EP0031260A3 (en) 1981-07-22
US4369561A (en) 1983-01-25
FR2472268B1 (OSRAM) 1983-10-14
EP0031260A2 (fr) 1981-07-01

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