FR2460037A1 - Procede d'auto-alignement de regions differemment dopees d'une structure de semi-conducteur - Google Patents

Procede d'auto-alignement de regions differemment dopees d'une structure de semi-conducteur Download PDF

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Publication number
FR2460037A1
FR2460037A1 FR7916055A FR7916055A FR2460037A1 FR 2460037 A1 FR2460037 A1 FR 2460037A1 FR 7916055 A FR7916055 A FR 7916055A FR 7916055 A FR7916055 A FR 7916055A FR 2460037 A1 FR2460037 A1 FR 2460037A1
Authority
FR
France
Prior art keywords
regions
layer
nitride
self
fact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7916055A
Other languages
English (en)
French (fr)
Other versions
FR2460037B1 (en:Method
Inventor
Marcel Roche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR7916055A priority Critical patent/FR2460037A1/fr
Priority to DE8080400815T priority patent/DE3062516D1/de
Priority to EP80400815A priority patent/EP0021931B1/fr
Priority to JP8385880A priority patent/JPS564278A/ja
Priority to US06/161,572 priority patent/US4311533A/en
Publication of FR2460037A1 publication Critical patent/FR2460037A1/fr
Application granted granted Critical
Publication of FR2460037B1 publication Critical patent/FR2460037B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H10P76/20—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H10P76/40—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/133—Reflow oxides and glasses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/137—Resists
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/145—Shaped junctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Transistors (AREA)
FR7916055A 1979-06-22 1979-06-22 Procede d'auto-alignement de regions differemment dopees d'une structure de semi-conducteur Granted FR2460037A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR7916055A FR2460037A1 (fr) 1979-06-22 1979-06-22 Procede d'auto-alignement de regions differemment dopees d'une structure de semi-conducteur
DE8080400815T DE3062516D1 (en) 1979-06-22 1980-06-06 Process for the self-alignment of differently doped regions of a semiconductor structure, and application of the process to the manufacture of a transistor
EP80400815A EP0021931B1 (fr) 1979-06-22 1980-06-06 Procédé d'auto-alignement de régions différemment dopées d'une structure de semiconducteur, et application du procédé à la fabrication d'un transistor
JP8385880A JPS564278A (en) 1979-06-22 1980-06-20 Centering method
US06/161,572 US4311533A (en) 1979-06-22 1980-06-20 Method of making self-aligned differently doped regions by controlled thermal flow of photoresist layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7916055A FR2460037A1 (fr) 1979-06-22 1979-06-22 Procede d'auto-alignement de regions differemment dopees d'une structure de semi-conducteur

Publications (2)

Publication Number Publication Date
FR2460037A1 true FR2460037A1 (fr) 1981-01-16
FR2460037B1 FR2460037B1 (en:Method) 1982-12-31

Family

ID=9226969

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7916055A Granted FR2460037A1 (fr) 1979-06-22 1979-06-22 Procede d'auto-alignement de regions differemment dopees d'une structure de semi-conducteur

Country Status (5)

Country Link
US (1) US4311533A (en:Method)
EP (1) EP0021931B1 (en:Method)
JP (1) JPS564278A (en:Method)
DE (1) DE3062516D1 (en:Method)
FR (1) FR2460037A1 (en:Method)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3173581D1 (en) * 1980-10-28 1986-03-06 Toshiba Kk Masking process for semiconductor devices using a polymer film
US4398964A (en) * 1981-12-10 1983-08-16 Signetics Corporation Method of forming ion implants self-aligned with a cut
JPS61127174A (ja) * 1984-11-26 1986-06-14 Toshiba Corp 半導体装置の製造方法
US4945067A (en) * 1988-09-16 1990-07-31 Xerox Corporation Intra-gate offset high voltage thin film transistor with misalignment immunity and method of its fabrication
US5618384A (en) * 1995-12-27 1997-04-08 Chartered Semiconductor Manufacturing Pte, Ltd. Method for forming residue free patterned conductor layers upon high step height integrated circuit substrates using reflow of photoresist
US6458656B1 (en) * 2000-03-16 2002-10-01 Advanced Micro Devices, Inc. Process for creating a flash memory cell using a photoresist flow operation
US20050042421A1 (en) * 2002-03-04 2005-02-24 Kurt Schwarzwalder Multi-layer polymer component, apparatus and method
US20030165660A1 (en) * 2002-03-04 2003-09-04 Kurt Schwarzwalder Polymer component, apparatus and method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1437781A (fr) * 1964-04-21 1966-05-06 Philips Nv Procédé pour appliquer sur un support des couches métalliques séparées par un interstice
DE2018027A1 (de) * 1969-04-15 1970-10-22 Tokyo Shibaura Electric Co. Ltd., Kawasaki (Japan) Verfahren zum Einbringen extrem feiner öffnungen
US3920483A (en) * 1974-11-25 1975-11-18 Ibm Method of ion implantation through a photoresist mask
FR2305022A1 (fr) * 1975-03-21 1976-10-15 Western Electric Co Procede de fabrication de transistors
EP0003733A1 (de) * 1977-12-05 1979-09-05 Siemens Aktiengesellschaft Verfahren zur Erzeugung abgestufter Fenster in Materialschichten aus Isolations- bzw. Elektrodenmaterial für die Herstellung einer integrierten Halbleiterschaltung und nach diesem Verfahren hergestellter MIS-Feldeffekttransistor mit kurzer Kanallänge

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USB311264I5 (en:Method) * 1964-12-31 1900-01-01
FR2241875B1 (en:Method) * 1973-08-21 1977-09-09 Radiotechnique Compelec
US3976524A (en) * 1974-06-17 1976-08-24 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
US4022932A (en) * 1975-06-09 1977-05-10 International Business Machines Corporation Resist reflow method for making submicron patterned resist masks
GB1545208A (en) * 1975-09-27 1979-05-02 Plessey Co Ltd Electrical solid state devices
US4201800A (en) * 1978-04-28 1980-05-06 International Business Machines Corp. Hardened photoresist master image mask process
JPS54147789A (en) * 1978-05-11 1979-11-19 Matsushita Electric Ind Co Ltd Semiconductor divice and its manufacture
US4253888A (en) * 1978-06-16 1981-03-03 Matsushita Electric Industrial Co., Ltd. Pretreatment of photoresist masking layers resulting in higher temperature device processing

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1437781A (fr) * 1964-04-21 1966-05-06 Philips Nv Procédé pour appliquer sur un support des couches métalliques séparées par un interstice
DE2018027A1 (de) * 1969-04-15 1970-10-22 Tokyo Shibaura Electric Co. Ltd., Kawasaki (Japan) Verfahren zum Einbringen extrem feiner öffnungen
US3920483A (en) * 1974-11-25 1975-11-18 Ibm Method of ion implantation through a photoresist mask
FR2305022A1 (fr) * 1975-03-21 1976-10-15 Western Electric Co Procede de fabrication de transistors
EP0003733A1 (de) * 1977-12-05 1979-09-05 Siemens Aktiengesellschaft Verfahren zur Erzeugung abgestufter Fenster in Materialschichten aus Isolations- bzw. Elektrodenmaterial für die Herstellung einer integrierten Halbleiterschaltung und nach diesem Verfahren hergestellter MIS-Feldeffekttransistor mit kurzer Kanallänge

Also Published As

Publication number Publication date
EP0021931A1 (fr) 1981-01-07
JPS564278A (en) 1981-01-17
EP0021931B1 (fr) 1983-03-30
FR2460037B1 (en:Method) 1982-12-31
US4311533A (en) 1982-01-19
DE3062516D1 (en) 1983-05-05

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