FR2455287A1 - Procede permettant le test d'un circuit integre - Google Patents

Procede permettant le test d'un circuit integre

Info

Publication number
FR2455287A1
FR2455287A1 FR8009417A FR8009417A FR2455287A1 FR 2455287 A1 FR2455287 A1 FR 2455287A1 FR 8009417 A FR8009417 A FR 8009417A FR 8009417 A FR8009417 A FR 8009417A FR 2455287 A1 FR2455287 A1 FR 2455287A1
Authority
FR
France
Prior art keywords
output
circuit
exclusive
door
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8009417A
Other languages
English (en)
Other versions
FR2455287B1 (fr
Inventor
Josephus Delvigne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of FR2455287A1 publication Critical patent/FR2455287A1/fr
Application granted granted Critical
Publication of FR2455287B1 publication Critical patent/FR2455287B1/fr
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31701Arrangements for setting the Unit Under Test [UUT] in a test mode

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

POUR IMPOSER UNE SITUATION DE TEST A UN CIRCUIT INTEGRE 1 QUE L'ON DESIRE CONTROLER, AU MOINS UNE SORTIE INTERNE DU CIRCUIT EST PROLONGEE VERS L'EXTERIEUR A TRAVERS UN ETAGE DE SORTIE 5, TANDIS QU'UNE ENTREE B ET UNE SORTIE A DUDIT ETAGE CONDUISENT, A L'INTERIEUR DU CIRCUIT, A UNE PORTE OU- EXCLUSIF 9. AUSSI LONGTEMPS QUE LA SORTIE 2 EST CHARGEE PAR UNE RESISTANCE FORTE, COMME C'EST LE CAS EN SITUATION DE FONCTIONNEMENT NORMAL DU CIRCUIT, LADITE PORTE OU- EXCLUSIF 9 ENGENDRE LE MEME SIGNAL QUEL QUE SOIT LE SIGNAL EN SORTIE. POUR PROCEDER AU TEST, ON FORCE LA SORTIE AVEC UNE IMPULSION OPPOSEE DE SORTE QUE LA SORTIE DE LA PORTE OU- EXCLUSIF CHANGE D'ETAT ET IMPOSE AU CIRCUIT 7-3 SA SITUATION DE TEST. LA PORTE OU- EXCLUSIF 9 PEUT ETRE SUIVIE D'UNE BASCULE BISTABLE, DE SORTE QUE POUR INSTAURER LA SITUATION DE TEST, IL SUFFIT DE DISPOSER D'UNE SEULE IMPULSION COMPLEMENTAIRE. APPLICATION: CIRCUITS INTEGRES A LOGIQUE SEQUENTIELLE.
FR8009417A 1979-04-27 1980-04-25 Procede permettant le test d'un circuit integre Granted FR2455287A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2917126A DE2917126C2 (de) 1979-04-27 1979-04-27 Verfahren zum Prüfen einer integrierten Schaltung und Anordnung zur Durchführung des Verfahrens

Publications (2)

Publication Number Publication Date
FR2455287A1 true FR2455287A1 (fr) 1980-11-21
FR2455287B1 FR2455287B1 (fr) 1983-09-23

Family

ID=6069439

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8009417A Granted FR2455287A1 (fr) 1979-04-27 1980-04-25 Procede permettant le test d'un circuit integre

Country Status (6)

Country Link
US (1) US4385275A (fr)
JP (1) JPS55149063A (fr)
CA (1) CA1164947A (fr)
DE (1) DE2917126C2 (fr)
FR (1) FR2455287A1 (fr)
GB (1) GB2049206B (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0084260A1 (fr) * 1981-12-29 1983-07-27 Fujitsu Limited Circuit intégré à semiconducteur avec circuit de test

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2943552A1 (de) * 1979-10-27 1981-05-21 Deutsche Itt Industries Gmbh, 7800 Freiburg Monolithisch integrierte schaltung
US4556840A (en) * 1981-10-30 1985-12-03 Honeywell Information Systems Inc. Method for testing electronic assemblies
AU8963582A (en) * 1981-10-30 1983-05-05 Honeywell Information Systems Incorp. Design and testing electronic components
US4808915A (en) * 1981-10-30 1989-02-28 Honeywell Bull, Inc. Assembly of electronic components testable by a reciprocal quiescent testing technique
US4502127A (en) * 1982-05-17 1985-02-26 Fairchild Camera And Instrument Corporation Test system memory architecture for passing parameters and testing dynamic components
GB8432305D0 (en) * 1984-12-20 1985-01-30 Int Computers Ltd Crystal oscillator overdrive
US4975641A (en) * 1988-07-14 1990-12-04 Sharp Kabushiki Kaisha Integrated circuit and method for testing the integrated circuit
KR950011803B1 (ko) * 1988-08-30 1995-10-10 금성일렉트론주식회사 테스트 모우드 기능 수행, 입력 회로
JPH0455779A (ja) * 1990-06-26 1992-02-24 Matsushita Electric Ind Co Ltd 電子回路装置
JPH0484782A (ja) * 1990-07-27 1992-03-18 Nec Corp テスト回路
US5982815A (en) * 1996-07-01 1999-11-09 Advanced Micro Devices Inc. Circuit for setting a device into a test mode by changing a first port to a fixed clock and a second port to a non-fixed clock

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2534502A1 (de) * 1975-08-01 1977-02-10 Siemens Ag Individuell pruefbarer, integrierter baustein
US4176258A (en) * 1978-05-01 1979-11-27 Intel Corporation Method and circuit for checking integrated circuit chips

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2330014A1 (fr) * 1973-05-11 1977-05-27 Ibm France Procede de test de bloc de circuits logiques integres et blocs en faisant application

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2534502A1 (de) * 1975-08-01 1977-02-10 Siemens Ag Individuell pruefbarer, integrierter baustein
US4176258A (en) * 1978-05-01 1979-11-27 Intel Corporation Method and circuit for checking integrated circuit chips

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0084260A1 (fr) * 1981-12-29 1983-07-27 Fujitsu Limited Circuit intégré à semiconducteur avec circuit de test
US4550289A (en) * 1981-12-29 1985-10-29 Fujitsu Limited Semiconductor integrated circuit device

Also Published As

Publication number Publication date
US4385275A (en) 1983-05-24
GB2049206A (en) 1980-12-17
CA1164947A (fr) 1984-04-03
GB2049206B (en) 1983-02-16
DE2917126A1 (de) 1980-10-30
JPS634151B2 (fr) 1988-01-27
DE2917126C2 (de) 1983-01-27
FR2455287B1 (fr) 1983-09-23
JPS55149063A (en) 1980-11-20

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Legal Events

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