FR2436444B1 - Systeme de multitraitement de donnees - Google Patents

Systeme de multitraitement de donnees

Info

Publication number
FR2436444B1
FR2436444B1 FR7922827A FR7922827A FR2436444B1 FR 2436444 B1 FR2436444 B1 FR 2436444B1 FR 7922827 A FR7922827 A FR 7922827A FR 7922827 A FR7922827 A FR 7922827A FR 2436444 B1 FR2436444 B1 FR 2436444B1
Authority
FR
France
Prior art keywords
processing system
data multi
data
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7922827A
Other languages
English (en)
Other versions
FR2436444A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Publication of FR2436444A1 publication Critical patent/FR2436444A1/fr
Application granted granted Critical
Publication of FR2436444B1 publication Critical patent/FR2436444B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
FR7922827A 1978-09-14 1979-09-12 Systeme de multitraitement de donnees Expired FR2436444B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53113937A JPS588018B2 (ja) 1978-09-14 1978-09-14 多重プロセッサシステム

Publications (2)

Publication Number Publication Date
FR2436444A1 FR2436444A1 (fr) 1980-04-11
FR2436444B1 true FR2436444B1 (fr) 1986-09-19

Family

ID=14624931

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7922827A Expired FR2436444B1 (fr) 1978-09-14 1979-09-12 Systeme de multitraitement de donnees

Country Status (3)

Country Link
US (1) US4308580A (fr)
JP (1) JPS588018B2 (fr)
FR (1) FR2436444B1 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58140862A (ja) * 1982-02-16 1983-08-20 Toshiba Corp 相互排他方式
US4698753A (en) * 1982-11-09 1987-10-06 Texas Instruments Incorporated Multiprocessor interface device
JPS6079460A (ja) * 1983-10-07 1985-05-07 Nec Corp 密結合多重演算装置における制御方式
US5261108A (en) * 1988-10-08 1993-11-09 Nec Corporation Multiprocessor communications register providing complete access in a full access mode, and mapped access in a partial access mode
US5175861A (en) * 1988-10-14 1992-12-29 Nec Corporation Lock processing system
JPH0394321A (ja) * 1989-06-21 1991-04-19 Hitachi Ltd アクセス制御方法
JP2503287B2 (ja) * 1990-04-05 1996-06-05 富士通株式会社 生存確認機能を持つ複合計算機
JP2785998B2 (ja) * 1990-05-18 1998-08-13 富士通株式会社 計算機システム
JPH0520250A (ja) * 1991-07-17 1993-01-29 Shikoku Nippon Denki Software Kk データ処理装置
JPH06250916A (ja) * 1993-02-26 1994-09-09 Fujitsu Ltd 共有メモリの排他制御方法
US5613139A (en) * 1994-05-11 1997-03-18 International Business Machines Corporation Hardware implemented locking mechanism for handling both single and plural lock requests in a lock message

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1218761B (de) * 1963-07-19 1966-06-08 International Business Machines Corporation, Armonk, N. Y. (V. St. A.) Datenspeidbereinrichtung
US3348210A (en) * 1964-12-07 1967-10-17 Bell Telephone Labor Inc Digital computer employing plural processors
US3469239A (en) * 1965-12-02 1969-09-23 Hughes Aircraft Co Interlocking means for a multi-processor system
US3528062A (en) * 1968-07-05 1970-09-08 Ibm Program interlock arrangement,including task suspension and new task assignment
US3551892A (en) * 1969-01-15 1970-12-29 Ibm Interaction in a multi-processing system utilizing central timers
US3760365A (en) * 1971-12-30 1973-09-18 Ibm Multiprocessing computing system with task assignment at the instruction level
JPS5311418B2 (fr) * 1973-09-26 1978-04-21
JPS5813932B2 (ja) * 1975-04-07 1983-03-16 株式会社日立製作所 記憶装置の多重使用制御方式
GB1536853A (en) * 1975-05-01 1978-12-20 Plessey Co Ltd Data processing read and hold facility
US4000485A (en) * 1975-06-30 1976-12-28 Honeywell Information Systems, Inc. Data processing system providing locked operation of shared resources

Also Published As

Publication number Publication date
JPS588018B2 (ja) 1983-02-14
US4308580A (en) 1981-12-29
FR2436444A1 (fr) 1980-04-11
JPS5539994A (en) 1980-03-21

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