FR2412889B1 - Systeme de traitement de donnees - Google Patents
Systeme de traitement de donneesInfo
- Publication number
- FR2412889B1 FR2412889B1 FR7836089A FR7836089A FR2412889B1 FR 2412889 B1 FR2412889 B1 FR 2412889B1 FR 7836089 A FR7836089 A FR 7836089A FR 7836089 A FR7836089 A FR 7836089A FR 2412889 B1 FR2412889 B1 FR 2412889B1
- Authority
- FR
- France
- Prior art keywords
- data processing
- processing system
- data
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
- G06F12/125—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list being generated by decoding an array or storage
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/863,637 US4229789A (en) | 1977-12-22 | 1977-12-22 | System for transferring data between high speed and low speed memories |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2412889A1 FR2412889A1 (fr) | 1979-07-20 |
FR2412889B1 true FR2412889B1 (fr) | 1985-10-18 |
Family
ID=25341457
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7836089A Expired FR2412889B1 (fr) | 1977-12-22 | 1978-12-22 | Systeme de traitement de donnees |
Country Status (5)
Country | Link |
---|---|
US (1) | US4229789A (fr) |
JP (1) | JPS5491153A (fr) |
DE (1) | DE2854782C2 (fr) |
FR (1) | FR2412889B1 (fr) |
GB (1) | GB2011135B (fr) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1601955A (en) * | 1977-10-21 | 1981-11-04 | Marconi Co Ltd | Data processing systems |
US4298929A (en) * | 1979-01-26 | 1981-11-03 | International Business Machines Corporation | Integrated multilevel storage hierarchy for a data processing system with improved channel to memory write capability |
EP0019358B1 (fr) * | 1979-05-09 | 1984-07-11 | International Computers Limited | Système hiérarchique de mémorisation de données |
DE2935135C2 (de) * | 1979-08-30 | 1983-01-20 | Siemens AG, 1000 Berlin und 8000 München | Schaltungsanordnung zum Verarbeiten von Daten in einer aus Zentralprozessor, Arbeitsspeicher und dazwischen angeordnetem Pufferspeicher bestehenden Datenverarbeitungsanlage |
US4481570A (en) * | 1981-08-07 | 1984-11-06 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Automatic multi-banking of memory for microprocessors |
US4899275A (en) * | 1985-02-22 | 1990-02-06 | Intergraph Corporation | Cache-MMU system |
US4860192A (en) * | 1985-02-22 | 1989-08-22 | Intergraph Corporation | Quadword boundary cache system |
US4884197A (en) * | 1985-02-22 | 1989-11-28 | Intergraph Corporation | Method and apparatus for addressing a cache memory |
US4933835A (en) * | 1985-02-22 | 1990-06-12 | Intergraph Corporation | Apparatus for maintaining consistency of a cache memory with a primary memory |
US5255384A (en) * | 1985-02-22 | 1993-10-19 | Intergraph Corporation | Memory address translation system having modifiable and non-modifiable translation mechanisms |
US4928239A (en) * | 1986-06-27 | 1990-05-22 | Hewlett-Packard Company | Cache memory with variable fetch and replacement schemes |
US5091846A (en) * | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
US5287485A (en) * | 1988-12-22 | 1994-02-15 | Digital Equipment Corporation | Digital processing system including plural memory devices and data transfer circuitry |
US5467460A (en) * | 1990-02-14 | 1995-11-14 | Intel Corporation | M&A for minimizing data transfer to main memory from a writeback cache during a cache miss |
US5159678A (en) * | 1990-06-11 | 1992-10-27 | Supercomputer Systems Limited Partnership | Method for efficient non-virtual main memory management |
JPH06175914A (ja) * | 1992-09-21 | 1994-06-24 | Eastman Kodak Co | メモリ管理装置 |
US6324411B1 (en) * | 1997-05-20 | 2001-11-27 | Telefonaktiebolaget Lm Ericsson (Publ) | Background software loading in cellular telecommunication systems |
US6963960B2 (en) * | 2003-03-25 | 2005-11-08 | Microsoft Corporation | System and method for kernel mode memory management having movable kernel objects |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB979632A (en) * | 1960-04-20 | 1965-01-06 | Nat Res Dev | Improvements in or relating to electronic digital computing machines |
BE629069A (fr) * | 1962-03-05 | |||
US3427592A (en) * | 1964-11-12 | 1969-02-11 | Ibm | Data processing system |
GB1124017A (en) * | 1964-12-17 | 1968-08-14 | English Electric Computers Ltd | Data storage apparatus |
GB1196752A (en) * | 1967-05-04 | 1970-07-01 | Int Computers Ltd | Improvements relating to Data Handling Arrangements. |
US3573750A (en) * | 1968-03-29 | 1971-04-06 | Nippon Electric Co | High-speed memory system |
US3541529A (en) * | 1969-09-22 | 1970-11-17 | Ibm | Replacement system |
FR116049A (fr) * | 1975-03-20 | |||
GB1548401A (en) * | 1975-10-08 | 1979-07-11 | Plessey Co Ltd | Data processing memory space allocation and deallocation arrangements |
US4008460A (en) * | 1975-12-24 | 1977-02-15 | International Business Machines Corporation | Circuit for implementing a modified LRU replacement algorithm for a cache |
-
1977
- 1977-12-22 US US05/863,637 patent/US4229789A/en not_active Expired - Lifetime
-
1978
- 1978-12-05 GB GB7847177A patent/GB2011135B/en not_active Expired
- 1978-12-19 DE DE2854782A patent/DE2854782C2/de not_active Expired
- 1978-12-21 JP JP15697278A patent/JPS5491153A/ja active Granted
- 1978-12-22 FR FR7836089A patent/FR2412889B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5491153A (en) | 1979-07-19 |
GB2011135A (en) | 1979-07-04 |
FR2412889A1 (fr) | 1979-07-20 |
DE2854782A1 (de) | 1979-06-28 |
GB2011135B (en) | 1982-03-17 |
US4229789A (en) | 1980-10-21 |
DE2854782C2 (de) | 1982-06-09 |
JPS6142303B2 (fr) | 1986-09-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
TP | Transmission of property | ||
ST | Notification of lapse |