FR2427738A1 - Control circuit for alarm system - has two time delays controlling initiation and termination of alarm signal - Google Patents
Control circuit for alarm system - has two time delays controlling initiation and termination of alarm signalInfo
- Publication number
- FR2427738A1 FR2427738A1 FR7816405A FR7816405A FR2427738A1 FR 2427738 A1 FR2427738 A1 FR 2427738A1 FR 7816405 A FR7816405 A FR 7816405A FR 7816405 A FR7816405 A FR 7816405A FR 2427738 A1 FR2427738 A1 FR 2427738A1
- Authority
- FR
- France
- Prior art keywords
- gate
- control circuit
- counter
- output
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/292—Modifications for introducing a time delay before switching in thyristor, unijunction transistor or programmable unijunction transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
Abstract
The electronic control circuit which is unlatched by a change in logic level of an input instruction signal includes a clock (3) providing a continuous pulse train, and a counter (9) receiving the clock pulses. A first NAND-gate (12) receives at its input (14) the instruction logic level signal, while its output (15) is connected to the counter (9) in order to start the counter when the level changes. A second NAND-gate (16) has one input (17) connected to the instruction signal, and the other input (18) connected to the counter output. A bistable circuit (20) is connected to the output of this gate in order to undergo a change of position when the second gate changes. A monostable circuit (28) having a predetermined recovery time is connected to the output of the second NAND-gate and to the bistable circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7816405A FR2427738A1 (en) | 1978-06-01 | 1978-06-01 | Control circuit for alarm system - has two time delays controlling initiation and termination of alarm signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7816405A FR2427738A1 (en) | 1978-06-01 | 1978-06-01 | Control circuit for alarm system - has two time delays controlling initiation and termination of alarm signal |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2427738A1 true FR2427738A1 (en) | 1979-12-28 |
Family
ID=9208949
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7816405A Withdrawn FR2427738A1 (en) | 1978-06-01 | 1978-06-01 | Control circuit for alarm system - has two time delays controlling initiation and termination of alarm signal |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2427738A1 (en) |
-
1978
- 1978-06-01 FR FR7816405A patent/FR2427738A1/en not_active Withdrawn
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |