FR2422206A1 - Systeme multiprocesseur - Google Patents

Systeme multiprocesseur

Info

Publication number
FR2422206A1
FR2422206A1 FR7908727A FR7908727A FR2422206A1 FR 2422206 A1 FR2422206 A1 FR 2422206A1 FR 7908727 A FR7908727 A FR 7908727A FR 7908727 A FR7908727 A FR 7908727A FR 2422206 A1 FR2422206 A1 FR 2422206A1
Authority
FR
France
Prior art keywords
module
multiprocessor system
processor
communication link
communication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7908727A
Other languages
English (en)
Other versions
FR2422206B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Publication of FR2422206A1 publication Critical patent/FR2422206A1/fr
Application granted granted Critical
Publication of FR2422206B1 publication Critical patent/FR2422206B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

La présente invention a trait à un système multiprocesseur comprenant plusieurs modules processeurs répartis le long d'une liaison de communication. Un tel système trouve notamment une application dans les terminaux électroniques aux points de vente. Un objet de la présente invention est de fournir un système multiprocesseur dans lequel l'accès de tous les modules est garanti à une liaison de communication qui leur est associée. Dans un système multiprocesseur conforme à l'invention, chaque module processeur comprend une interface de communication 24 qui est couplée à un bus de communication intermodule 10 et à un processeur central 21 de ce module et qui est disposée pour assurer l'émission et la réception de messages entre ce module processeur et un autre module. Chaque unité d'interface a la possibilité d'envoyer un caractère de message sur ledit bus pendant une tranche de temps prescrite et répétitive affectée à ce module.
FR7908727A 1978-04-06 1979-04-06 Systeme multiprocesseur Granted FR2422206A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/893,856 US4223380A (en) 1978-04-06 1978-04-06 Distributed multiprocessor communication system

Publications (2)

Publication Number Publication Date
FR2422206A1 true FR2422206A1 (fr) 1979-11-02
FR2422206B1 FR2422206B1 (fr) 1985-01-25

Family

ID=25402231

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7908727A Granted FR2422206A1 (fr) 1978-04-06 1979-04-06 Systeme multiprocesseur

Country Status (7)

Country Link
US (1) US4223380A (fr)
JP (1) JPS6024499B2 (fr)
CA (1) CA1115803A (fr)
DE (1) DE2913288C2 (fr)
FR (1) FR2422206A1 (fr)
GB (1) GB2019069B (fr)
YU (1) YU79379A (fr)

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Also Published As

Publication number Publication date
DE2913288C2 (de) 1985-01-10
JPS54139352A (en) 1979-10-29
DE2913288A1 (de) 1979-10-11
GB2019069A (en) 1979-10-24
US4223380A (en) 1980-09-16
CA1115803A (fr) 1982-01-05
JPS6024499B2 (ja) 1985-06-13
YU79379A (en) 1982-06-30
GB2019069B (en) 1982-07-07
FR2422206B1 (fr) 1985-01-25

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TP Transmission of property
ST Notification of lapse