FR2406912A1 - Pulse sequence generation for memory testing - uses reverse counter supplied with starting values by its own memory - Google Patents

Pulse sequence generation for memory testing - uses reverse counter supplied with starting values by its own memory

Info

Publication number
FR2406912A1
FR2406912A1 FR7829353A FR7829353A FR2406912A1 FR 2406912 A1 FR2406912 A1 FR 2406912A1 FR 7829353 A FR7829353 A FR 7829353A FR 7829353 A FR7829353 A FR 7829353A FR 2406912 A1 FR2406912 A1 FR 2406912A1
Authority
FR
France
Prior art keywords
memory
pulse sequence
sequence generation
counter
starting values
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7829353A
Other languages
French (fr)
Other versions
FR2406912B1 (en
Inventor
Dieter E Staiger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE2746743A external-priority patent/DE2746743C2/en
Priority claimed from DE2829709A external-priority patent/DE2829709C2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2406912A1 publication Critical patent/FR2406912A1/en
Application granted granted Critical
Publication of FR2406912B1 publication Critical patent/FR2406912B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/78—Generating a single train of pulses having a predetermined pattern, e.g. a predetermined number
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G01R31/31921—Storing and outputting test patterns using compression techniques, e.g. patterns sequencer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

The process for the generation of pulse sequences which are not separated from each other in time is used for testing a memory. When a specific numerical value has been attained, pulse generation is initiated by a degressive counter which is controlled by clock pulses. The degressive counter may receive a starting value from a memory. Before the specific value has been attained, the resetting of the counter at a new starting value, also provided by the memory, is carried out. This occurs at the instant when the counter would normally have attained the value of zero in its program of counting.
FR7829353A 1977-10-18 1978-10-09 Pulse sequence generation for memory testing - uses reverse counter supplied with starting values by its own memory Granted FR2406912A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2746743A DE2746743C2 (en) 1977-10-18 1977-10-18 Method and arrangement for the computer-controlled generation of pulse intervals
DE2829709A DE2829709C2 (en) 1978-07-06 1978-07-06 Method and arrangement for generating pulse cycles immediately following one another in time

Publications (2)

Publication Number Publication Date
FR2406912A1 true FR2406912A1 (en) 1979-05-18
FR2406912B1 FR2406912B1 (en) 1982-06-04

Family

ID=25772918

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7829353A Granted FR2406912A1 (en) 1977-10-18 1978-10-09 Pulse sequence generation for memory testing - uses reverse counter supplied with starting values by its own memory

Country Status (2)

Country Link
JP (2) JPS6042421B2 (en)
FR (1) FR2406912A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3023699A1 (en) * 1980-06-25 1982-01-14 Ibm Deutschland Gmbh, 7000 Stuttgart METHOD AND ARRANGEMENT FOR GENERATING IMPULSES AT PRESET TIME RELATION WITHIN PRESET IMPULSE INTERVALS WITH HIGH TIME RESOLUTION
JPS61172431A (en) * 1985-01-28 1986-08-04 Fujisoku:Kk Sampling signal generating circuit
JPS63145529U (en) * 1987-03-17 1988-09-26

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
EXBK/76 *
EXBK/77 *
EXBK/78 *

Also Published As

Publication number Publication date
JPS6042421B2 (en) 1985-09-21
JPS5511693A (en) 1980-01-26
FR2406912B1 (en) 1982-06-04
JPS5465463A (en) 1979-05-26
JPS6042422B2 (en) 1985-09-21

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Legal Events

Date Code Title Description
ST Notification of lapse