JPS61172431A - Sampling signal generating circuit - Google Patents

Abstract

PURPOSE:To generate a high speed sampling signal by frequency-dividing a basic signal outputted from an oscillation circuit to generate a required clock signal and retarding the clock signal by a programmable digital delay circuit thereby using a comparatively low speed. CONSTITUTION:A sampling signal generating circuit is formed by providing an oscillation means 43 generating a basic signal in response to a trigger signal, a frequency-dividing means 44 frequency-dividing the basic signal into a prescribed period of clock signal, a down counter 46 applying down count by using a numeral set in response to the clock signal and means 49, 51 to which a prescribed delay shorter than the period of the basic signal is set, where the output signal of the down counter is delayed in response to the delay to generate a sampling signal. Thus, circuit elements with comparatively low speed are used to simplify the circuit constitution and low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sampling signal generation circuit used in, for example, a sampling oscilloscope.

[Technical background of the invention and its problems]

As is well known, for example, a sampling circuit used in a sampling oscilloscope needs to sequentially delay its sampling timing with respect to a trigger signal. As such a sampling signal generation circuit,
Conventionally, analog circuits based on a combination of sawtooth waves and staircase waves,
Alternatively, two methods are being considered: digital circuits using counters, etc.

In the case of analog circuits, their configurations are complex and require advanced circuit technology, while in the case of digital circuits, while they can be used with almost no adjustment, their operating speeds are limited. Since the operating speed of the integrated circuit is limited, it is difficult to increase the speed of the integrated circuit.

[Purpose of the invention]

This invention was made based on the above-mentioned circumstances.
The purpose is to be able to generate high-speed sampling signals using relatively low-speed circuits, and to
The present invention aims to provide a sampling signal generation circuit with a relatively simple circuit configuration.

[Summary of the invention]

The present invention generates a required clock signal by frequency-dividing a basic signal output from multiple oscillator circuits, and delays the clock signal using a programmer digital delay circuit. This generates an equivalent sampling signal with a period shorter than the period of .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 7 shows the main parts of a sampling oscilloscope to which the present invention is applied. Channel 1. Input signals i, , i, respectively corresponding to channel 2 are supplied to attenuators (ATT) J 1 and J 2, respectively. These attenuators 11 and 12 are used to appropriately set the level tubes of the input signals i, , i, using operators (not shown), and the nine set values ATS corresponding to the operations of the operators are as follows. ! 5 and the like to an arithmetic processing unit (hereinafter abbreviated as CPU) 31. The input signals attenuated to a predetermined level by these attenuators 11 and 12 are sent to amplifiers 13 and 13, respectively.
Sample and hold (S”) circuit 15.16 through 14
supplied to These sample and hold circuits 15, 1
6 is supplied with a sampling signal 8p from a sampling signal generation circuit to be described later, and the input signal is sampled by this sampling signal Sp.

These sampled signals are each input to an amplifier 17.
18 is supplied to the transducer 1yexoK, D, ~D
, into an 8-bit digital signal. These converters 19°20 receive the sampled signal fA/
A write signal WR input into the D converter 19.20 and read signals chJRD and ah2RD for reading out the converted digital signal from the converter 19.20 are supplied, and from these converters 19.20, An interrupt signal 4 lNTR indicating the end of the conversion operation is output. Further, the output signals of the amplifiers 13 and 14 are supplied to a trigger signal generation circuit 21. This trigger signal generating circuit 21 is set by a selection switch 22 and outputs a trigger signal TRG when the output signal of the selected one of the nine levels and the output signal of the amplifier 13 or 14 matches. The sampling signal Sp is generated based on this trigger signal TRG.

On the other hand, FIG. 8 shows the entire control circuit. The arithmetic processing unit (hereinafter abbreviated as CPU) 31 is composed of, for example, a micro combinator.
ROM J4 is connected to JJ via a data bus 32 and an address bus 33.

RAM 35, address decoder 36. ! Haport 3
1 is connected. The ROM 34 stores programs and data for controlling the operation of the sampling signal generation circuit, etc. jj), and the RAM 35 stores the φ
Digital signals from converters 19, 20 and said attenuator 11. lj! A set value AT8 is stored. Further, the address decoder 36 outputs the read signal ehJ.
RDechJRD*Load signal LOAD used to clear Kakunta, etc., clock selection signals cK and 8EL that specify the selection of the four-way clock signal, delay selection signal DELEYSEL that specifies the selection of the delay amount, and reset that resets the up counter. signal RESET, count-up signal UP for counting up the up counter;
C+1 force is output. @Vc%I10) J7 is the setting value A'l'S of the attenuator 11.12.

An output signal of the selection switch 38 for setting the sweep time, a busy signal BUSY indicating that the trigger signal TRG is in a waiting state, and the like are supplied.

Next, the tinging signal generation circuit, which is the main part of the present invention, will be explained.

In FIGS. 1 and 2, connectors 40 and 41 are used to connect the signals described above. The start circuit 42 is a flip-flop circuit (hereinafter abbreviated as FF circuit) 42
&v42be inverter circuit 42c, NAND circuit 4jd
In response to the reset output signal of the FF circuit 42& output in response to the load signal LOAD, the contents of the up counter 47, which will be described later, are loaded into the down counter 46, and the oscillation circuit 43, which will be described later, is stopped, and the FF circuit The Pizzey signal BUSY is completely sent out from the circuit 48, and furthermore, the frequency dividing circuit 44 is cleared by the set output signal. Further, the oscillation circuit 43 operates according to a reset output signal of the FF circuit 4ja output in response to the trigger signal TRG.

The oscillation circuit 43 includes a crystal oscillator 43a and an inverter circuit 43
b, 43c, a NAND circuit 43d, and resistors 4Je and 4Jf, for example, outputs a basic signal of 25 MEz. The frequency dividing circuit 44 is 10. The frequency dividing circuit 44 is 10.
Frequency divider 44b.

10-' frequency divider 44celO frequency divider 44d.

10-5 frequency divider 44, 1/2 frequency divider 44 f t 1
15 frequency divider 44g and selection circuit (multiple frequencyer) 4
4b and 441, the basic signal is frequency-divided to generate a required clock signal CK. The clock selector 45 is connected to the selector circuit 45 and the CPU
Clock selection data is taken in based on the four clock selection signals CK and SEL supplied from J1, and the selection circuits 44f and 44g of the frequency dividing circuit 44 are controlled according to this selection data, and the required clock signal CK is controlled. This is taken out from the frequency dividing circuit 44.

The down counter 46 is composed of 4-pit counters 46g and 46b connected in series, and receives the load signal LOA.
counting the clock signal outputted from the frequency dividing circuit 44 until the value (delay amount) supplied to the up counter 4r by the signal outputted from the start circuit 42 in response to D;
It is delayed. The up counter 41 is composed of an 8-pit counter 41, and is connected to the CPU J1.
Reset signal RE8ET
It is now reset by FF circuit 4
8 is a load signal L supplied from the start circuit 42.
It is set by a signal corresponding to OAD K, and this set output is supplied to the CPH as a busy signal BUSY.

Further, the FF circuit 48 is cleared by the output signal of the down counter 46, and this clear output signal is supplied to the digital delay circuit 49.

This digital delay circuit 49 is a digital delay element 49
It is composed of a. This digital delay element 4
9m is set to 35 times in 5 ns increments by a 3-bit setting signal.
! The input signal can be delayed up to II. The delay selector 50 is constituted by a selection circuit 50a, and selects delay data (DT) according to a delay selection signal DELEY 8EL supplied from the CPU JJ.
is input into the digital delay circuit 49 as the setting signal.
It is intended to supply

The sampling signal generation circuit 51 includes an FF circuit 51a that generates a sampling signal Sp from the output signal of the digital delay circuit 50, an inverter circuit 51b, and a resistor 5.
1c, capacitor 51d, NAND circuit 51e,
A write signal generation circuit 51f that generates a write signal 6 slightly delayed from the sampling signal 5, a NAND circuit 51TKe51b, an inverter circuit 511, and a resistor 51j.
, from the capacitor 51k), the converter 1!1,2
The clear circuit sxL generates an interrupt signal lNTR indicating the end of 0 conversion and a clear signal for the FF circuit 511.

In the above configuration, first, the selection switch 3 shown in FIG.
The operation when, for example, the sweep time is set to 1 μm using 811C will be explained.

In the CPU 31, first, in step SI shown in FIG. 3, the delayed data storage area DT is cleared.

After this, the sweep times S and T set in steps s and tss e84 are determined, and the delay data of 4, 2, and 1 is stored in the storage area nK in Stella 7''8seSs-8, according to the determination result. In this case, the sweep times S, T.

is step 8. , S, and esa, 0 is stored in the storage area n in step S. After this, in step S, the reset signal RESE
T is output, the up counter 41 is reset, and step S1. The delay data stored in the storage area DT is set in the delay selector 50. next,
In step S8, clock selection data is set in the clock selector 45. This clock selection data is stored in the ROM J4, and its values are set as shown in FIG. In this case, since the sweep time is 1 μm, the clock selection data is @OO''.After this, in step S□, the load signal LOAD is
is sent out, the frequency divider 441 of the frequency dividing circuit 44 is activated by the output signal of the FF circuit 42m of the start circuit 42.
44g is cleared, and the reset output signal causes the contents of the up counter 41 to be set to "0" in the down counter 46.Furthermore, the oscillation circuit 43 is stopped, and the set output terminal Q of the FF circuit 48 is cleared. A high-level busy signal BUSY is output from the CPU 31, and the CPU 31 is placed in a standby state in step S.

In this state, the trigger signal generation circuit 21 generates a trigger signal T in response to the input signal (1) as shown in FIG.
When RG is output, the oscillation circuit 43 is operated by the reset output signal of the FF circuit 4J& in the start circuit 42, and the basic signal output from the oscillation circuit 43 is supplied to the frequency dividing circuit 44. The frequency dividing circuit 44 outputs a clock signal CK of 40 ns as shown in FIG. 5 according to the clock selection data set in the clock selector 45.
supplied to

As described above, this down counter 46 is shaded with @0'', so the ?low signal B1 is output as shown in FIG. 5 in response to the first clock signal CKK. Accordingly, the reset output signal of the FF circuit 48 becomes high level as shown by Fl in FIG.
1 is supplied to a digital delay circuit 49.

This digital delay circuit 49 has delay data @00″,
That is, since the delay time @0'' is set, the signal indicated by 0 in FIG. 5 is output from the output terminal 0. Therefore, the sampling signal SPs shown in FIG. 5 is output from the reset output terminal Q of the FF circuit JJa.

This signal is cut off from being supplied to the sample and hold circuits 15 and 16, and the level of the input signal 110 at the time the trigger signal TRG starts is extracted, as shown in FIG.

On the other hand, the set output signal of the FF circuit 51m is supplied to the write signal generation circuit sit, and in this write signal generation circuit 51tflC, as shown in FIG.
is generated.

This write signal WR is supplied to the converter 19,2 (j), and the signal extracted in the sample and hold circuit 15.16 by this write signal WR is output to the converter 19.
20.

When the conversion operation of this φ converter 19#jO is completed, an interrupt signal 1NTR1@eINT is generated as shown in FIG.
R, □ are output, and these interrupt signals lNTR11eI
NTR, , is supplied to the clear circuit 5ztK. In this clear circuit 511, as shown in FIG.
A clear signal CL1 delayed by a predetermined time is generated based on the FF R, and this clear signal CL1 is
It is supplied to the clear terminal of the circuit 51a. Therefore, the FF circuit 51a is reset and the sampling signal S
Ps is stopped.

However, when the trigger signal TRG is supplied to the start circuit 42, the set output signal of the FF circuit 48 is set to a low level by the reset signal of the FF circuit 4ja. Therefore, in the CPU s J, control is performed from step S to Stella f8. ．． It is then opened and stopped for 100 μS. This time is the time until the conversion operation of the converters 19 and 20 is completed. Thereafter, in step S1°, read signals chJRD and cb'RD are sequentially output, and the converted data of the converters 1y and 20 are read into the RAM 35 in response to the signals chJRD and ehJRD. Next, step S8. The contents of storage area n are added to the contents of storage area DT. In this case, the contents of both storage areas [)T and n are @0'', so
The contents of the storage area DT remain @0''. The contents of this storage area DT are set in the delay selector 50 at the stellar f S, y, and after this, at step 818, the contents of the delay selector 50 are set to @0''. O” or not. In this case, since it is @02, step S1. The UP, C+1 signal is output at the up counter 47.
The content of is incremented by 1+1''.Next, in step S, it is determined whether the content of this 7 tsuzo kakunta 47 is 1256'', and if it has not reached @256'', control is transferred to step S. .

Hereinafter, in the same manner, each time the up counter 47 counts up, the down counter 46 outputs multiple outputs, but the timing of the low signals B, , B, . . . is the clock signal 1.
It will be delayed one by one. Therefore, the sampling signal Sp* * 8 output from the sampling signal generation circuit 51
Similarly, ps"" is also output with a delay. Therefore, the sampling period of the input signal i1 is the trigger signal T
RG Yo F) 40 ns e 80 ns t 120
ns- and lag behind. And up counter 41
When the content reaches @256', the sampling and previous conversion operations are finished, and a display operation (not shown) is performed.

Next, a case where the sweep time is set to 25 ns, for example, will be described. In this case, first, after the storage area DT is cleared in step S□, Stella ff3. @l'' is set in the storage area].Next, in step S, a reset signal REMIT is output and the up counter 4
1 is reset, and step S8. The delay data 10' stored in the storage area DT is set in the delay selector 50. After this, in step SK1, the clock selection data @OO'' is sent to the clock selector 45.
is set. Then, when the load signal LOAD is sent out in response to Stella 7'S, the start circuit 42
The set output signal of the FF circuit 4ja clears the frequency dividers 44a to 44g of the frequency dividing circuit 440 in the same manner as described above, and the content 10m of the up counter 41 is set in the down counter 46 by the reset output signal. Further, the 1 oscillation circuit 43 is stopped, a high-level busy signal BUOY is output from the output terminal Q of the FF circuit 480, and the CPU 3J is placed in a standby state in step S.

In this state, when the trigger signal TRG is output in response to the input signal i1 as shown in FIG. and the basic signal is output. This basic signal is supplied to a frequency divider circuit 44, and from this frequency divider circuit 44, according to the clock selection data set in the clock selector 48, as shown in FIG.
A clock signal CK of 40m- is output. As described above, this clock signal CK is supplied to the down counter 46 in which @0'' is set. Therefore, in response to the first clock signal CK, the clock signal CK is supplied to the down counter 46 as shown in FIG. In response to this signal B, the reset output signal of the FF circuit 48 becomes high level as shown by Fi in FIG.
is supplied to a digital delay circuit 49. Since the delay data "oo", that is, the delay time 10'' is set in the digital delay circuit 451, the signal indicated by 01 in FIG. 6 is output from the output terminal 0. This signal is supplied to the clock input terminal of the FF circuit 51a in the sampling signal generation circuit 51.

Therefore, the sampling signal SPt shown in FIG. 6 is output from the reset output terminal Q of the FF circuit 51h. This signal is supplied to sample and hold circuits Is and 1g, and as shown in FIG. 6, the level of input signal il at the time of generation of trigger signal TRG is extracted.

On the other hand, in response to the set output signal of the FF circuit 51&, the write signal generating circuit 51f generates a write signal W shown in FIG.
R, is generated and extracted by the write signal WR1 in the sampling hold circuit 15.16, and a running signal is written into the transducer 19.20. This φ converter 19, 20
When the conversion operation is completed, interrupt signals lNTR1, #rNTR, 1 are output as shown in FIG. 6, and a clear signal CL1 shown in FIG. Consequently, the FF circuit 51a is reset by this clear signal CL.

However, when the trigger signal TRG is supplied to the start circuit 42, the control is transferred from step S to step 814 as described above (in the CPU j J, the control is transferred from step S to step 814, and the opening and stopping of 100JI is performed.After this, step S, , the conversion data of the converters 19 and 20 is read into the RAM J j K. Next, in step S4, the contents of the storage area DT are added to the contents of the storage area DT. In this case, the contents of the storage area n Since the content of is "1" as described above, the content of storage area DT is @l#.

The contents of this storage area DT are stored in step S8. is set in the delay selector 50 in step S8. It is determined whether the content of the delay selector 50 is @0''.

In this case, since it is "1", it is determined in step S8 whether the content of the up counter 47 is @256', and if it has not reached @256', the control is transferred to step S11.

Thereafter, steps 8111 to S3. Each time the clock signal CK is outputted, the control is transferred to the mekunkakunta 46 and the signal 20-signal B.

B, . . . are output, and the FF circuit 48 outputs reset output signals F, , F, . The digital delay circuit 49 outputs reset output signals F, , Fs of 5.
"I e 10 nm"-delayed as 0, . 0.・
...A signal is obtained. This signal 0, . 0. ... is supplied to the sampling signal generation circuit 51, and the sampling signal generation circuit 51 outputs the sampling signal SPt e Sp* delayed by the trigger signal TRG (F) 5 ns y 10 ns as shown in FIG. Ru.

After going through the loop of steps S and ~sue eight times, the memory area DTO value becomes @8'', that is, a binary number @1000'' at step 81, and the delay selector 5, which has a 3-bit configuration, is reached. The output signal of is @ooo'. Therefore, the multi-control in step 811 is performed by Stella f8.
m, and the value of the up counter 47 is incremented. In this way, when the content of the up counter 41 becomes @256'', the sampling and conversion operations are completed, and a display operation (not shown) is performed.

According to the above embodiment, when the sweep time is 0.5 μS or less, the clock signal is sequentially delayed by a predetermined time by the digital delay circuit 49, and the sampling signal is generated based on the delayed signal. Finally, the basic signal of 25 WEx (clock signal C of 40 as
K) It is capable of generating an equivalent sampling signal with a higher period (up to 5n1).

In addition, since the basic signal of the oscillation circuit can be set as low as 25 MHz, relatively low-speed circuit elements can be used, making it possible to simplify the circuit configuration and reduce costs. be.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without changing the gist.

〔Effect of the invention〕

As described above in detail, according to the present invention, it is possible to generate a high-speed sampling signal using a relatively low-speed circuit, and it is also possible to provide a sampling signal generation circuit with a relatively simple circuit configuration. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the sampling signal generation circuit according to the present invention, FIG. 2 is a circuit block diagram specifically showing FIG. 1, and FIG. 3 is for explaining the operation of the arithmetic processing device. 4 is a diagram showing the relationship between sweep time and clock selection data, FIGS. 5 and 6 are waveform diagrams of various parts shown to explain the operation of the sampling signal generation circuit, and FIG. 7 is a diagram showing the relationship between sweep time and clock selection data. , and FIG. 8 are configuration diagrams showing the main parts of a sampling oscilloscope to which the present invention is applied. 15, x6...sample hold circuit, 19°20.
... Me converter, 21... Trigger signal generation circuit, 31.
... CPUt 42 ... Start circuit, 43 ... Oscillator circuit, 44 ... Frequency divider circuit, 45 ... Four-way selector, 46 ... Run counter, 41 ... Aggregation circuit, 48 ... - FF circuit, 49... digital delay circuit, 50... delay selector, 51... sampling signal generation circuit. Representative Patent Attorney Takehiko Suzue Figure 1 Figure 3 (a) Figure 3 (b) Figure 4 Figure 6

Claims (1)

[Claims] oscillating means for generating a basic signal in response to a trigger signal; frequency dividing means for dividing the generated basic signal into a clock signal having a predetermined cycle; A down counter that counts down from a numerical value, and a means for generating a sampling signal by setting a predetermined delay amount shorter than the period of the basic signal and delaying the output signal of the down counter according to the delay amount. A sampling signal generation circuit characterized by: